The distance transform (DT) is a general operator forming the basis of many methods in computer vision and geometry, with great potential for practical applications. However, all the optimal algorithms for the computation of the exact Euclidean DT (EDT) were proposed only since the 1990s. In this work, state-of-the-art sequential 2D EDT algorithms are reviewed and compared, in an effort to reach more solid conclusions regarding their differences in speed and their exactness. Six of the best algorithms were fully implemented and compared in practice.

2D Euclidean distance transform algorithms: A comparative survey

The distance transform (DT) is a general operator forming the basis of many methods in computer vision and geometry, with great potential for practical applications. However, all the optimal algorithms for the computation of the exact Euclidean DT (EDT) were proposed only since the 1990s. In this work, state-of-theart sequential 2D EDT algorithms are reviewed and compared, in an effort to reach more solid conclusions regarding their differences in speed and their exactness. Six of the best algorithms were fully implemented and compared in practice.

2 2D Euclidean Distance Transform Algorithms: A Comparative Survey

To estimate the configuration of a figure in a captured image, a silhouette image of the figure is scanned to create a signed distance image. This image identifies the distance of each pixel in the image to the closest edge of the silhouette, and indicates whether the pixel is inside or outside of the silhouette. Multiple distance images of this type are employed to generate an eigen-points model, which provides an affine mapping from the signed distance images to the limb parameters of an authored skeleton. When a new input image is received, it is first processed to create the signed-distance image, and this image is applied to the eigen-points model to estimate limb parameters, such as the locations of various joints in the figure. From this information, each foreground pixel in the captured image can be assigned to one of the limbs.

Method and system for estimating jointed-figure configurations

This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform module, we employ the polyphase decomposition technique and the coefficient folding technique to the decimation filters of stages 1 and 2, respectively. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are 100% hardware utilization, fast computing time (0.5-0.67 times of the parallel filters'), regular data flow, and low control complexity, making this architecture suitable for next generation image compression systems, e.g., JPEG-2000.

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An efficient architecture for two-dimensional discrete wavelet transform

Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worst-case design assumptions and resynchronization of asynchronous external inputs. In practice, however, many asynchronous design methods suffer from a number of problems: unsound algorithms (implementations may have hazards), harsh restrictions on the range of designs that can be handled (single-input changes only), incompatibility with existing design styles and inefficiency in the resulting circuits.
This thesis presents a new locally-clocked design method for the synthesis of asynchronous controllers. The method has been automated, is proven correct and produces high-performance implementations which are hazard-free at the gate-level. Implementations allow multiple-input changes and handle a relatively unconstrained class of behaviors (called "burst-mode" specifications). The method produces state-machine implementations with a minimal or near-minimal number of states. Implementations can be easily built in such common VLSI design styles as gate-array, standard cell and full-custom. Realizations typically have the latency of their combinational logic.
A complete set of state and logic minimization algorithms has been developed and automated for the synthesis method. The logic minimization algorithm differs from existing algorithms since it generates two-level minimized logic which is also hazard-free.
The synthesis program is used to produce competitive implementations for several published designs. In addition, a large real-world controller is designed as a case study: an asynchronous second-level cache controller for a new RISC processor.

Automatic synthesis of burst-mode asynchronous controllers

A fast algorithm for Euclidean distance maps of a 2-D binary image

A synthesis method for multiple-input change asynchronous sequential machines is proposed. The method is based on the self-synchronization principle. The internal states are realized with edge-sensitive flip-flops which are triggered selectively. The new concept of selective triggering or controlled excitation results in considerable saving in logic and more flexible design. The state assignment is arbitrary, and the number of state variables required can be made absolutely minimum. A detailed comparison of the speed of operation is made with one of the well-known methods of realization. It is found that our realization is, in general, as fast, and sometimes could be even faster.

Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops

Fast Hough transform on a mesh connected processor array

The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. In this paper, we present a parallel pipelined VLSI array architecture for 2D dyadic separable DWT. The 2D data array is partitioned into non-overlapping groups of rows. All rows in a partition are processed in parallel, and consecutive partitions are pipelined. Moreover, multiple wavelet levels are computed in the same pipeline, and multiple DWT problems can be pipelined also. The whole computation requires a single scan of the image data array. Thus, it is suitable for on-line real-time applications. For anN×N image, anm-level DWT can be computed in $$\tfrac{{N^2 }}{{2_q }} + 2^{m - 1} (2p + 3)$$ time units on a processor costing no more than $$\tfrac{8}{3}(C_m + C_u )p(p + 2q)$$ , whereq is the partition size,p is the length of corresponding 1D DWT filters,Cm andCa are the costs of a parallel multiplier and a parallel adder respectively, and a time unit is the time for a multiplication and an addition. Forq=N ? m, the computing time reduces to $$\frac{N}{2}$$ . When a large number of DWT problems are pipelined, the computing time is about $$\tfrac{{N^2 }}{{2_q }}$$ per problem.

VLSI architecture for fast 2D discrete orthonormal wavelet transform

The Euclidean distance transform (EDT) converts a binary image into one where each pixel has a value equal to its Euclidean distance to the nearest foreground pixel. It has important uses in image analysis, computer vision, and robotics where high speed computation is essential. In this paper, a sequential algorithm which does not require global operations is first presented. We then apply a sequence of algorithm transformations to convert it into a parallel algorithm for mesh-connected SIMD computers. For an n × n image on an equal-sized processor array, the time complexity is O(n). An algorithm for computing large EDT problems on smaller processor arrays is also given. For an n × n image on a g × g processor array, the time complexity is O((n2g) log(ng)).

Henry Y. H. Chuang

Papers

A fast algorithm for Euclidean distance maps of a 2-D binary image

Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops

Fast Hough transform on a mesh connected processor array

VLSI architecture for fast 2D discrete orthonormal wavelet transform

An efficient algorithm for complete Euclidean distance transform on mesh-connected SIMD