Electrons have a charge and a spin, but until recently these were considered separately. In classical electronics, charges are moved by electric fields to transmit information and are stored in a capacitor to save it. In magnetic recording, magnetic fields have been used to read or write the information stored on the magnetization, which 'measures' the local orientation of spins in ferromagnets. The picture started to change in 1988, when the discovery of giant magnetoresistance opened the way to efficient control of charge transport through magnetization. The recent expansion of hard-disk recording owes much to this development. We are starting to see a new paradigm where magnetization dynamics and charge currents act on each other in nanostructured artificial materials. Ultimately, 'spin currents' could even replace charge currents for the transfer and treatment of information, allowing faster, low-energy operations: spin electronics is on its way.

/pdf/the-emergence-of-spin-electronics-in-data-storage-1vrnm5549k.pdf

The emergence of spin electronics in data storage

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In an MRAM, a current with high current density flows in a line in write operation. When write operation is to be performed with respect to a memory cell existing at the intersection of a write word line and a bit line, a current flows in the write word line from a WWL driver to a voltage down converter. Thereafter, a current flows in the write word line in a direction opposite to the direction of the current flowing in the write operation, i.e., from the voltage down converter to the WWL driver. The same applies to a bit line. For example, after write operation, a current flows in the bit line in a direction opposite to the direction of a current flowing in the write operation.

Magnetic random access memory

In this paper, recent developments in magnetic tunnel junctions (MTJs) are reported with their potential impacts on integrated circuits. MTJs consist of two metal ferromagnets separated by a thin insulator and exhibit two resistances, low (Rp) or high (Rap) depending on the relative direction of ferromagnet magnetizations, parallel (P) or antiparallel (AP), respectively. Tunnel magnetoresistance (TMR) ratios, defined as (Rap $Rp)/Rp as high as 361%, have been obtained in MTJs with Co40Fe40B20 fixed and free layers made by sputtering with an industry-standard exchange-bias structure and post deposition annealing at Ta = 400 degC. The corresponding output voltage swing DeltaV is over 500 mV, which is five times greater than that of the conventional amorphous Al-O-barrier MTJs. The highest TMR ratio obtained so far is 500% in a pseudospin-valve MTJ annealed at Ta = 475 degC, showing a high potential of the current material system. In addition to this high-output voltage swing, current-induced magnetization switching (CIMS) takes place at the critical current densities (JCO) on the order of 106 A/cm2 in these MgO-barrier MTJs. Furthermore, high antiferromagnetic coupling between the two CoFeB layers in a synthetic ferrimagnetic free layer has been shown to result in a high thermal-stability factor with a reduced JCO compared to single free-layer MTJs. The high TMR ratio enabled by the MgO-barrier MTJs, together with the demonstration of CIMS at a low JCO, allows development of not only scalable magnetoresistive random-access memory with feature sizes below 90 nm but also new memory-in-logic CMOS circuits that can overcome a number of bottlenecks in the current integrated-circuit architecture

/pdf/magnetic-tunnel-junctions-for-spintronic-memories-and-beyond-2tm3rrxd78.pdf

Magnetic Tunnel Junctions for Spintronic Memories and Beyond

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times. >

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

A magnetic random access memory circuit comprises first and second row decoders receiving a part of a given address, first and second column decoders receiving the other part of a given address, a plurality of pairs of sense lines connected between output terminals of the first row decoder and output terminals of the second row decoder, each pair of sense lines being located adjacent to each other, a plurality of word lines connected between output terminals of the first column decoder and output terminals of the second column decoder, and extending to intersect the sense lines so that intersections of the sense lines and the word lines are located in the form of a matrix. A memory array includes a plurality of cell pairs distributed over the matrix, each cell pair including a memory cell and a reference cell located adjacent to each other. Each of the memory cell and the reference cell includes a magneto-resistive element. The memory cell and the reference cell of each cell pair are located at intersections of one word line and one pair of sense lines, respectively. The memory cell of the each cell pair is connected between one sense line of the one pair of sense lines and the one word line, and the reference cell of the each cell pair is connected between the other sense line of the one pair of sense lines and the one word line.

Magnetic random access memory circuit

A method of manufacturing a magnetic random access memory for excluding stress-induced defects in memory cells. The method is composed of forming a first magnetic film over a substrate, forming a tunnel insulating film on the first magnetic film such that the tunnel insulating film has a curvature, forming a second magnetic film on the tunnel insulating film, and etching the first magnetic film, the tunnel insulating film and the second magnetic film to form a memory cell. The etching is executed such that the curvature is excluded from the memory cell.

Method of fabricating magnetic random access memory operating based on tunnel magnetroresistance effect

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

A 512kb MRAM comprising cross-point cells, magnetic tunnel junctions, bit lines and word lines is designed using a 0.25/spl mu/m CMOS and a 0.6/spl mu/m MRAM process. The design provides a new sensing method without a large area overhead despite a low current cross-point signal. The MRAM operates with read access time of 1.0/spl mu/s at 2.5V.

http://ieeexplore.ieee.org/iel5/8736/27661/01234300.pdf

Hideaki Numata

Papers

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

Magnetic random access memory circuit

Method of fabricating magnetic random access memory operating based on tunnel magnetroresistance effect

High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

A 512kb cross-point cell MRAM