Magnetic resonance imaging apparatus

A system for optimizing customer utility usage in a utility network of customer sites, each having one or more utility devices, where customer site is communicated between each of the customer sites and an optimization server having software for optimizing customer utility usage over one or more networks, including private and public networks. A customer site model for each of the customer sites is generated based upon the customer site information, and the customer utility usage is optimized based upon the customer site information and the customer site model. The optimization server can be hosted by an external source or within the customer site. In addition, the optimization processing can be partitioned between the customer site and an external source.

Energy optimization system

A highly scalable application network appliance is described herein. According to one embodiment, a network element includes a switch fabric, a first service module coupled to the switch fabric, and a second service module coupled to the first service module over the switch fabric. In response to packets of a network transaction received from a client over a first network to access a server of a data center having multiple servers over a second network, the first service module is configured to perform a first portion of OSI (open system interconnection) compatible layers of network processes on the packets while the second service module is configured to perform a second portion of the OSI compatible layers of network processes on the packets. The first portion includes at least one OSI compatible layer that is not included in the second portion. Other methods and apparatuses are also described.

Highly scalable architecture for application network appliances

A system and method of detecting an aberrant message is provided. An ordered set of words within the message is detected. The set of words found within the message is linked to a corresponding set of expected words, the set of expected words having semantic attributes. A set of grammatical structures represented in the message is detected, based on the ordered set of words and the semantic attributes of the corresponding set of expected words. A cognitive noise vector comprising a quantitative measure of a deviation between grammatical structures represented in the message and an expected measure of grammatical structures for a message of the type is then determined. The cognitive noise vector may be processed by higher levels of the neural network and/or an external processor.

Intelligent control with hierarchical stacked neural networks

A microprocessor based electric actuator control system is provided which allows accurate determination of the forces opposing movement of manipulator driveshaft. The control system electronically sets a predetermined current through an actuator to produce an electromagnetic force. A displacement measuring device, in conjunction with a time clock measures velocity and calculates acceleration of the actuator in response to the current. The force on the shaft is computer varied such that the acceleration is determined. For the acceleration to be zero, the electromagnetic force be exactly balanced by forces equal but opposite in magnitude. Since the force value is determined by the computer, the opposing force is also accurately determined with no external sensing device needed.

Program controlled force measurement and control system

A parallel data processing system performs a data processing by using a plurality of data processing units, namely, processor elements, synchronously. The parallel data processing system comprises a plurality of data processing units, a plurality of trays, and a clock generator. The plurality of trays are connected to respective data processing units and have a function of storing a plurality of data and a function of transmitting the data. The clock generator is producing a clock so that the data transfer between the trays and between the trays and the data processing units, and the data processing in the data processing unit is executed synchronously. Data are transferred between trays during the period in which they are processed, thus substantially eliminating the data transmission time. Furthermore, the interim result of the operation is stored in the tray and thus when the later operation needs the interim result, the interim result stored in the tray is efficiently used without the need to access the memory provided in the data processing apparatus.

Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data

A parallel data processing system processes data by synchronously operating a plurality of data processing units (processor elements). It aims at reducing the overhead caused by the data transmission in a system, performing a matrix operation and a neurocomputer operation by making the best of its parallel processing method, and at using excess units for another operation when the number of units required for an operation is smaller than the number of the existing units. The parallel data processing system comprises a plurality of data processing units; a plurality of trays which store and transmit data, each connected to a data processing unit; a tray connection switching unit for changing the connection state of the data transmission path between trays, dividing data processing units into a plurality of groups, and performing an independent operation on each group; and a clock generator for synchronously operating a data transmission between trays and a data process in a data processing unit. Thus, the data are transmitted while the data are processed, so the data transmission time can be actually counted as zero.

Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time

A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated

Signal processing device accessible as memory

The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first configuration data to be supplied, a network in which all inputs and outputs of a plurality of said processor elements are connected and which transfers data by one clock between the input and output according to second configuration data to be supplied, and a switching unit which cyclically switches by one clock and supplies the first and second configuration data prepared for the given number of tasks to each of the processing units.

Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths. The delay adjustment are based on the results of a measurement by the delay measuring unit, so that the time elapsing while the signal is propagated from the predetermined position to the plurality of processors, through the respective signal paths for supplying the signal to the processors, are equal.

Hideki Yoshizawa

Papers

Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data

Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time

Signal processing device accessible as memory

Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

Parallel data processing apparatus with signal skew compensation