Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

The invention is a system for providing virtual connections through an ATM interworking multiplexer on a call-by-call basis. A signaling processor receives signaling for a call and selects the virtual connection for the call. The signaling processor generates new signaling that identifies the selection and transfers the new signaling to the ATM interworking multiplexer that accepted the access connection for the call. The multiplexer converts user information from the access connection into ATM cells for transmission over the virtual connection in accord with the new signaling.

Broadband telecommunications system

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Data processing device and method

Data processing method and device

The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first configuration data to be supplied, a network in which all inputs and outputs of a plurality of said processor elements are connected and which transfers data by one clock between the input and output according to second configuration data to be supplied, and a switching unit which cyclically switches by one clock and supplies the first and second configuration data prepared for the given number of tasks to each of the processing units.

Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of controlling a processing cycle and the velocity of an operating clock and attaining improvement in processing efficiency and the reduction of power consumption in signal processing based on one-instruction/one-cycle processing such as DSP. SOLUTION: This DSP is provided with a decoder 11 for fetching and decoding an instruction, an arithmetic part 12 for executing prescribed arithmetic processing according to the fetched instruction, a clock generating part 13 for generating the operating clock having the prescribed processing cycle based on a reference clock previously supplied from the outside, a processing cycle setting means 16 for setting the processing cycle to be a reference based on the contents of signal processing instructed by the instruction and the number of processing cycles for every signal processing, and a memory 14 for reading/ writing data through a bus 15 in the prescribed processing cycle based on the generated operating clock.

Signal processing circuit

An echo canceller system for performing echo cancelling processing on a plurality of cells on a transmission line includes a plurality of echo canceller units to which the cells applied to the echo canceller system are allocated according to an applied order of the cells regardless of channels of the cells

Echo canceller system in an ATM network

PROBLEM TO BE SOLVED: To provide a reconfigurable circuit capable of time-division multiplexing in which time losses due to configuration switching and the latency of data input/output are reduced SOLUTION: The reconfigurable circuit capable of time-division multiplexing comprises a plurality of processor elements each having a pipeline structure where the number of steps is an integral multiple of a given number, and each having a process part whose configuration is variable depending on first configuration data supplied; a network to which all the inputs and outputs of the plurality of processor elements are connected so that data transfers between the inputs and the outputs are carried out in one clock; and a switch means for supplying to each of the processing part the configuration data prepared for the predetermined number of tasks, in such a way that the configuration data are periodically switched in one clock COPYRIGHT: (C)2006,JPO&NCIPI

Reconfigurable circuit capable of time-division multiplexing

The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with register renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, register renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors.

Teruo Ishihara

Papers

Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

Signal processing circuit

Echo canceller system in an ATM network

Reconfigurable circuit capable of time-division multiplexing

STRAIGHT: hazardless processor architecture without register renaming