CHAPTER 1: INTRODUCTION What is Power Quality? Power Quality -- Voltage Quality Why Are We Concerned About Power Quality? The Power Quality Evaluation Procedure Who Should Use This Book Overview of the Contents CHAPTER 2: TERMS AND DEFINITIONS Need for a Consistent Vocabulary General Classes of Power Quality Problems Transients Long-Duration Voltage Variations Short-Duration Voltage Variations Voltage Imbalance Waveform Distortion Voltage Fluctuation Power Frequency Variations Power Quality Terms Ambiguous Terms CBEMA and ITI Curves References CHAPTER 3: VOLTAGE SAGS AND INTERRUPTIONS Sources of Sags and Interruptions Estimating Voltage Sag Performance Fundamental Principles of Protection Solutions at the End-User Level Evaluating the Economics of Different Ride-Through Alternatives Motor-Starting Sags Utility System Fault-Clearing Issues References CHAPTER 4: TRANSIENT OVERVOLTAGES Sources of Transient Overvoltages Principles of Overvoltage Protection Devices for Overvoltage Protection Utility Capacitor-Switching Transients Utility System Lightning Protection Managing Ferroresonance Switching Transient Problems with Loads Computer Tools for Transients Analysis References CHAPTER 5: FUNDAMENTALS OF HARMONICS Harmonic Distortion Voltage versus Current Distortion Harmonics versus Transients Harmonic Indexes Harmonic Sources from Commercial Loads Harmonic Sources from Industrial Loads Locating Harmonic Sources System Response Characteristics Effects of Harmonic Distortion Interharmonics References Bibliography CHAPTER 6: APPLIED HARMONICS Harmonic Distortion Evaluations Principles for Controlling Harmonics Where to Control Harmonics Harmonic Studies Devices for Controlling Harmonic Distortion Harmonic Filter Design: A Case Study Case Studies Standards of Harmonics References Bibliography CHAPTER 7: LONG-DURATION VOLTAGE VARIATIONS Principles of Regulating the Voltage Devices for Voltage Regulation Utility Voltage Regulator Application Capacitors for Voltage Regulation End-User Capacitor Application Regulating Utility Voltage with Distributed Resources Flicker References Bibliography CHAPTER 8: POWER QUALITY BENCHMARKING Introduction Benchmarking Process RMS Voltage Variation Indices Harmonics Indices Power Quality Contracts Power Quality Insurance Power Quality State Estimation Including Power Quality in Distribution Planning References Bibliography CHAPTER 9: DISTRIBUTED GENERATION AND POWER QUALITY Resurgence of DG DG Technologies Interface to the Utility System Power Quality Issues Operating Conflicts DG on Distribution Networks Siting DGDistributed Generation Interconnection Standards Summary References Bibliography CHAPTER 10: WIRING AND GROUNDING Resources Definitions Reasons for Grounding Typical Wiring and Grounding Problems Solutions to Wiring and Grounding Problems Bibliography CHAPTER 11: POWER QUALITY MONITORING Monitoring Considerations Historical Perspective of Power Quality Measuring Instruments Power Quality Measurement Equipment Assessment of Power Quality Measurement Data Application of Intelligent Systems Power Quality Monitoring Standards References Index INDEX

Electrical Power Systems Quality

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

An RFID webstock containing a relatively high pitch-density array of semiconductive chips is provided and joined to a web bearing relatively widely spaced antennas in a continuous process. The RFID webstock is separated or cut into individual chip sections, with the spacing of the chips being increased as the RFID webstock is die cut. The individual chips on the sections are then joined to corresponding antennas to form an RFID inlay stock. This process is conducive to high speed roll-to-roll production of RFID tag and label roll stock.

Rfid label technique

Purpose – The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.Design/methodology/approach – This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.Findings – A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3...

Overview and outlook of through‐silicon via (TSV) and 3D integrations

A semiconductor device includes a first-first conductivity type semiconductor layer which includes a cell region portion and a junction terminating region portion, the junction terminating region portion being a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field; a second first conductivity type semiconductor layer which is formed on one surface of the first-first conductivity type semiconductor layer; a first main electrode which is electrically connected to the second-first conductivity type semiconductor layer; first-second conductivity type semiconductor layers which are formed in the cell region portion of the first-first conductivity type semiconductor layer in substantially vertical directions to the one surface of the first-first conductivity type semiconductor layer, respectively, and which are periodically disposed in a first direction which is an arbitrary direction parallel to the one surface; a second-second conductivity type semiconductor layer which is selectively formed in the other surface portion of the first-first conductivity type semiconductor layer so as to contact the first-second conductivity type semiconductor layers; a third-first conductivity type semiconductor layer which is selectively formed in the surface portion of the second-second conductivity type semiconductor layer; a second main electrode which is formed so as to contact the second-second conductivity type semiconductor layer and the third first conductivity type semiconductor layer; a control electrode which is formed on the surface of the first-first conductivity type semiconductor layer sandwiched by the adjacent second-second conductivity type semiconductor layers, the surface of the adjacent second-second conductivity type semiconductor layers and the surface of the third-first conductivity type semiconductor layer, with a gate insulating film interposed therebetween; and third-second conductivity type semiconductor layers which are formed in the junction terminating region portion and are periodically disposed in at least one direction of the first direction and a second direction perpendicular to the first direction

Semiconductor device and method of manufacturing semiconductor device

A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Stacked electronic component and manufacturing method thereof

A semiconductor device includes a semiconductor substrate with an electrode pad on a main surface of the semiconductor substrate; a first penetrating electrode which includes a through hole formed through the semiconductor substrate in the thickness direction so as to reach a metallic bump formed on the electrode pad, an insulating resin formed to fill the through hole in and a conductor formed in the through hole with insulated from the semiconductor substrate by the insulating resin and electrically to connect the electrode pad and the rear surface of the semiconductor wafer; a semiconductor chip mounted on the rear surface of the semiconductor wafer so that a rear surface of the semiconductor chip is faced to the rear surface of the semiconductor wafer; and a wiring to electrically connect the first penetrating electrode and an electrode formed on the semiconductor chip.

Semiconductor device and method for fabricating the same

A wafer transfer apparatus for sticking a wafer, which is divided into a multiplicity of chips and which has its surface stuck with a protective tape, to a ring frame by a transfer tape, includes: a positioning unit capable of disposing the protective tape stuck wafer on a positioning table and capable of performing a position adjustment of the wafer in longitudinal, lateral and rotational directions, so that the wafer is located in a reference position; a transfer tape mount unit capable of disposing the protective tape stuck wafer, which has been located in the reference position by the positioning unit, on a transfer tape mount table, and capable of sticking a transfer tape to both a ring frame disposed round periphery of the wafer and back of the wafer, so that the wafer and the ring frame are stuck to each other and integrated; and a protective tape peeling unit capable of disposing the wafer, which has its back covered with the transfer tape and which has been integrated with the ring frame by the transfer tape mount unit, on a protective tape peeling table, and capable of bonding an end of a peeling tape to an end of the protective tape stuck to the wafer surface, and capable of pulling the peeling tape so that the protective tape is peeled from the wafer surface.

Wafer transfer apparatus

By preventing warping of chips when detaching individual chips from a dicing sheet, improvement in quality without cracks and in productivity is realized. A collet (115) used in a step of detaching chips (110) discretely divided as bonded to a dicing sheet (109) from the dicing sheet has a flat attraction surface made of a porous material of a size equal to or larger than the chip size. Alternatively, the collet may have a chip attraction groove containing poles, balls or hemispheres, for example, to prevent warping of chips. In the step of detaching each chip from the dicing sheet, a means for reducing the bonding force of the dicing sheet, such as heating device or cooling device, may be provided. Thus, warping or cracking can be prevented in a process of thinned semiconductor substrate. Additionally, since the means for reducing the bonding force of the dicing sheet is provided in a semiconductor manufacturing equipment, breakage or cracking of chips can be prevented more reliably.

Hideo Numata

Papers

Semiconductor device and method of manufacturing semiconductor device

Stacked electronic component and manufacturing method thereof

Semiconductor device and method for fabricating the same

Wafer transfer apparatus

Semiconductor manufacturing equipment