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Hisashi Kaneko

Researcher at Toshiba

Publications -  93
Citations -  1533

Hisashi Kaneko is an academic researcher from Toshiba. The author has contributed to research in topics: Layer (electronics) & Semiconductor device. The author has an hindex of 22, co-authored 93 publications receiving 1531 citations. Previous affiliations of Hisashi Kaneko include Ebara Corporation & Tokyo Electron.

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Patent

Polishing agent and polishing method using the same

TL;DR: In this paper, the authors present a polishing method including the steps of forming a film made of material containing a metal as a main component over a substrate having depressed portions on a surface thereof so as to fill the depressed portions with the film, and polishing the film by a chemical mechanical polishing.
Patent

Semiconductor device and method of manufacturing semiconductor device

TL;DR: A semiconductor device includes a first-first conductivity type semiconductor layer which includes a cell region portion and a junction terminating region portion, the junction terminating region portion being a region portion which is positioned in an outer periphery of the cell region to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.
Patent

Eddy current loss measuring sensor, thickness measuring system, thickness measuring method, and recorded medium

TL;DR: In this article, the authors proposed a thickness measuring system consisting of an exciting coil for receiving high frequency current to excite a high frequency magnetic field, and a receiving coil for outputting the high-frequency current which is influenced by an eddy current loss caused by the current.
Patent

Method for production of semiconductor device

TL;DR: In this article, a method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing the semiconductor substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line.
Patent

Semiconductor device manufacturing method and semiconductor device

TL;DR: In this paper, a semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconducting substrate, and forming a lower level wiring in the trench, and then forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, and finally, a wiring trench in which at least the hard mask is exposed.