Dataflow machines are programmable computers of which the hardware is optimized for fine-grain data-driven parallel computation. The principles and complications of data-driven execution are explained, as well as the advantages and costs of fine-grain parallelism. A general model for a dataflow machine is presented and the major design options are discussed.Most dataflow machines described in the literature are surveyed on the basis of this model and its associated technology. For general-purpose computing the most promising dataflow machines are those that employ packet-switching communication and support general recursion. Such a recursion mechanism requires an extremely fast mechanism to map a sparsely occupied virtual space to a physical space of realistic size. No solution has yet proved fully satisfactory.A working prototype of one processing element is described in detail. On the basis of experience with this prototype, some of the objections raised against the dataflow approach are discussed. It appears that the overhead due to fine-grain parallelism can be made acceptable by sophisticated compiling and employing special hardware for the storage of data structures. Many computing-intensive programs show sufficient parallelism. In fact, a major problem is to restrain parallelism when machine resources tend to get overloaded. Another issue that requires further investigation is the distribution of computation and data structures over the processing elements.

http://web.cecs.pdx.edu/~alaa/ece588/papers/veen_acmcs_1986.pdf

Dataflow machine architecture

Data-flow refers both to a language-level paradigm of computation and to a family of processor architectures based on this paradigm. This article elaborates data-flow language issues and the evolution of data-flow languages. In considering limits to the expressive power of these languages, underlying architectural issues are discussed. Although the article attempts to present a complete history of data-flow languages, it concentrates on those languages that specifically belong to this class and have been implemented for a data-flow machine. In many cases, the distinctions between issues of language semantics and machine architecture are unclear. Usually we have found that this reflects the evolution of data-flow, and the close association between language and architecture development. In some sections of the article, it may appear that there is an imbalance in the amount of detail presented when compared with other sections. This imbalance is proportional to the publications and the amount of information readily available for the topics. >

A history of data-flow languages

A 4-Kb (128 words/spl times/32 bits) CMOS associative-memory large-scale integration (LSI) is described. This LSI has all the functions necessary to achieve a self-operative high-speed data search system. Garbage data collection capabilities have been built into the chip in order to develop self-operative systems. The chip's paralleled and pipelined multiple-response resolver makes high-speed, high-throughput data retrieval possible. On-chip extension capabilities for word length and count simplify attainment of a large associative memory system. A newly developed cell circuit allows for simultaneous parallel-writing operation for multiple words. This LSI, which is fabricated using 3-/spl mu/m and double-aluminium-layer CMOS process technology, has a 140-ns measured minimum cycle time and 250-mW measured power dissipation at 5-MHz operation.

A 4-Kbit associative memory LSI

An execution model that supports program reantrancy, recurslon, and automatic run-time loop unravelling is described. This execution model Is based on queue machines that execute acyclic data-flow graphs. The use of separate instruction and data token spaces allows program reentrancy. Execution environments called contexts execute acyclic data-flow graphs associated with high-level code blocks. Iteration and function activation are implemented by the dynamic creation of contexts and do not require the use of tagged tokens. A multiprocessor architecture that supports this execution model is proposed. T ~ system architecture is based on a partitioned ring in which each partition of the ring is a conventional processor/memory bus. The proposed architecture has bean simulated in software. A number of test programs have been developed and their execution on the proposed architecture has been evaluated. The performance of the proposed architecture with various numbers of processing elements is described. In addition, a number of task scheduling algorithms are presented and evaluated.

Data flow on a queue machine

The architecture of a data flow machine, called DFM, is developed for parallel list processing. The DFM can maximally exploit parallelism inherent in list processing, due to its ultra-multi-processing mechanism, packet communication-based parallel and pipeline execution mechanism, and lenient cons mechanism. A practical DFM implementation is described. A DFM prototype machine is implemented and DFM performance is evaluated in a simulation on the register transfer level using several benchmark programs. The DFM single processor system is shown to be about five times faster than conventional machines which use the same device technology, while a multi-processor DFM system is shown to achieve a linear speed-up ratio of 0.6 ~ 0.9.

Implementation and evaluation of a list-processing-oriented data flow machine

This paper analyzes some issues concerning list processing under a data flow control environment from the viewpoint of parallelism and also presents a new type of list-processing-oriented data flow machine, based on an association memory and logic-in-memory.The mechanism of partial execution in each function is shown by example to be effective in exploiting the parallelism in list processing. The lenient cons mechanism is shown to exploit maximally parallelism among activated functions.

A list-processing-oriented data flow machine architecture

List Processing with a Data Flow Machine

This paper describes some issues of parallel list processing under data flow control. Also a new type of list-processing oriented data flow machine is presented which achieves pipelined processing among activated functions. Performance evaluation through software simulation gave the following conclusions.



(1) This machine can utilize a high degree of parallelism even for simple programs due to the partial function-body execution and lenient cons effects.



(2) Parallel processing overhead does not affect the processing time.



(3) Memory contention is reduced by dividing the structure memory into many banks and by uniformly distributing cons operations in each bank.

Hirohide Mikami

Papers

A list-processing-oriented data flow machine architecture

List Processing with a Data Flow Machine

A list-processing-oriented data flow machine architecture and its evaluation

A Data Flow Machine Architecture for Highly Parallel Symbol Manipulations

List Processing with a Data Flow Machine.