The kinetics of silicide growth are classified into three different categories: (a) diffusion controlled, (b) nucleation controlled, (c) others (reaction rate controlled). These are analyzed with the aim of understanding both the phenomenology of growth and the specific atomic mechanisms of phase formation. Diffusion-controlled growth is discussed with respect to the Nernst-Einstein equation. Stress relaxation is considered as a possible cause of reaction-rate control. The relative merits of two different types of marker experiments are compared. A few silicides are discussed in terms of what can be inferred about diffusion mechanisms. The competition between reaction-rate and diffusion control phenomena is shown to have specific effects on the sequence of phase formation; it is also related to the formation of some amorphous compounds. Reactions between silicon and alloyed metal films are used to illustrate the respective influences of mobility and driving force factors on the kinetics of silicide growth; they can also be used to underline the dominance of nucleation over diffusion in some silicide formation processes.

Kinetics of formation of silicides: A review

A new method is proposed to electrically determine MOS transistor channel length with both accuracy and convenience. Based on the linear region relationship between effective channel length L eff and channel resistance R chan of an MOS transistor, this method determines L eff by applying relatively large but constant gate voltage to eliminate threshold voltage determination and takes into account external resistance. Comparison of this method with SEM measurement shows very good agreement (within ±0.1 µm resolution limit of our SEM technique).

A new method to determine MOSFET channel length

A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

Near‐noble metals react with Si to form a metal‐rich silicide at 100 to 200 °C. Growth of the silicide is selected by the criterion that diffusion of near‐noble metal atoms to the silicide‐silicon interface is needed in order to maintain a high interface mobility. Structure of the metal‐rich silicide facilitates the diffusion. It has been postulated that high interface mobility can be achieved by transforming Si atoms at the interface from covalent bonding to metallic bonding and the transformation can be induced by forming metal interstitials in Si.

Selective growth of metal‐rich silicide of near‐noble metals

Structure and growth kinetics of Ni2Si on silicon

An accurate and convenient method to determine an effective MOSFET channel length is proposed. This method is based on a computer aided evaluation of an intrinsic MOSFET channel resistance without using special test devices. N-channel silicon-gate MOSFETs were fabricated, and the channel length and its range of device to device scatter were evaluated . To define an effective channel, a simple model of the source-drain (S-D) diffusion layer is proposed. This model shows that the expected transition layer resistance between the S-D diffusion layer and the inverted channel layer agrees with the experimental results. The accuracy of this method is also discussed. It is found to be better than 0.1 µm.

https://iopscience.iop.org/article/10.1143/JJAP.18.953/pdf

A New Method to Determine Effective MOSFET Channel Length

Identifications of microscopic compositions in alloyed layers of heat‐treated Pt–Si contacts and analysis of chemical kinetics of solid‐solid reactions between Pt and Si have been carried out. The layer structure of the Pt–Si contact sequentially changes, through Pt–Pt2Si–Si, Pt–Pt2Si–PtSi–Si, and Pt2Si–PtSi–Si, into PtSi–Si during heat treatment at temperatures ranging from 200 to 500 °C. The rate‐determining step of the solid‐solid reaction in the Pt–Si system is the interdiffusion process of Pt and Si. The rate constants are well represented by the following Arrhenius relationships: kPt2Si=1.5×10−3 exp(−24 100/RT) cm2/sec and kPtSi=2.5×10−1 exp(−33 900/RT) cm2/sec.

Solid‐Solid Reactions in Pt–Si Systems

A semiconductor device obtains in which a silicide film of 3d, 4d and 5d transition metal such as iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), palladium (Pd), platinum (Pt), or the like, is used as a conductive means in place of the conventional simple metal and whose structure is semiconductor-insularsilicide.

Mos device with a metal-silicide gate

Annealed platinum-silicon contact electrical properties have been consistently investigated at the range of 6.0×1015~8.5×1019 cm-3 silicon carrier concentration ND and in the 200~700°C annealing temperature range. For diodes heat-treated at 300°C, having ND=6×1015 cm-3, nearly ideal Schottky barrier diodes are obtained. For ND≥7×1018 cm-3, ohmic contact is obtained. The situation is almost unchanged for up to the 500°C annealing temperature. However, by heat-treatment at above 600°C, the effective barrier height rapidly decreases and the carrier concentration range. Which yield ohmic contact characteristics, moves to lower values. These phenomena are satisfactorily interpreted on terms of "impurity pile up effect". The impurities pile-up is revealed by the Auger electron spectroscopy analysis. Arsenic impurities are piled up at the platinum silicide-silicon interface. Presumably, piled up impurities near PtSi–Si interface are electrically activated at above the 600°C annealing temperture. Effectively, the interface carrier concentration is increased by about one order of magnitude in regard to the silicon substrate carrier concentration by 600°C annealing.

https://iopscience.iop.org/article/10.1143/JJAP.17.1089/pdf

Electrical Properties of Platinum-Silicon Contact Annealed in an H 2 Ambient

A high speed, fully static, 1024 word by 4 bit Random Access Memory has been developed, using Diffusion Self Aligned (DSA) MOS transistors as active devices. The present RAM operates on a single power supply of 5 (±1) volt without internal bias generator. Its typical performances are; 57 ns access time, 100 ns cycle time and 520 mW operating power. The device was also confirmed to operate satisfactorily in the battery back up mode with 4.4 mW (VDD=1.1v) power dissipation.

Hiroki Muta

Papers

A New Method to Determine Effective MOSFET Channel Length

Solid‐Solid Reactions in Pt–Si Systems

Mos device with a metal-silicide gate

Electrical Properties of Platinum-Silicon Contact Annealed in an H 2 Ambient

High Speed 4k Static RAM Using DSA MOST's