An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A projection exposure apparatus including an irradiation optical system including a light source and irradiating a mask with irradiation light beams, a projection optical system for projecting an image of a pattern of the mask on a substrate, a plurality of first fly-eye type optical integrators each having an emission side focal plane disposed on a Fourier transformed surface with respect to the pattern of the mask in the irradiation optical system or on a plane adjacent to the same and having a center located at a plurality of positions which are eccentric from the optical axis of the irradiation optical system, a plurality of second fly-eye type optical integrators each having an emission side focal plane disposed on a Fourier transformed plane with respect to the incidental end of each of a plurality of the first fly-eye type optical integrators or on a plane adjacent to the same and being disposed to correspond to a plurality of the first fly-eye type optical integrators, and a light divider for dividing and causing the irradiation light beams from the light source to be incident on each of a plurality of the second fly-eye type optical integrators.

Projection exposure apparatus

The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

Lithography is a field in which advances proceed at a swift pace. This book was written to address several needs, and the revisions for the second edition were made with those original objectives in mind. Many new topics have been included in this text commensurate with the progress that has taken place during the past few years, and several subjects are discussed in more detail. This book is intended to serve as an introduction to the science of microlithography for people who are unfamiliar with the subject. Topics directly related to the tools used to manufacture integrated circuits are addressed in depth, including such topics as overlay, the stages of exposure, tools, and light sources. This text also contains numerous references for students who want to investigate particular topics in more detail, and they provide the experienced lithographer with lists of references by topic as well. It is expected that the reader of this book will have a foundation in basic physics and chemistry. No topics will require knowledge of mathematics beyond elementary calculus.

Principles of Lithography

Publisher Summary Catalytic oxidation of carbon monoxide over catalysts from the platinum group metals has been investigated. Apart from its enormous practical importance, this reaction is considered to proceed through a relatively simple mechanism because only diatomic molecules are involved and product formation occurs presumably only over a very few steps. This chapter discusses the adsorptive properties of the reactants, their mutual interaction, and the mechanism and kinetics of product formation as well as the investigations with well defined single-crystal surfaces. The activity of a catalyst for a particular reaction is strongly dependent on the surface structure. Directive investigation of the influence of the surface structure on the catalytic activity was performed by using a platinum single crystal whose surface was curved in such a way that not only the plane but also vicinals with varying step density of two different crystallographic directions were present.

Elementary Steps in the Catalytic Oxidation of Carbon Monoxide on Platinum Metals

A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.

Chip connection structure having diret through-hole connections through adhesive film and wiring substrate

A clock signal supply system is disclosed for a semiconductor device with a semiconductor chip and a wiring substrate connected in flip-chip fashion and an optical waveguide interposed in the space between electrode members, in which the mutual arrangement of the electrical interconnection and the optical waveguide interconnection on the wiring substrate is not affected and can be used separately from each other for different applications, thereby improving the throughput of the interconnections as a whole. In order to distribute a very fast clock signal beyond a 1 GHz in particular without any phase deviation in the clock signal supply system, a clock distributor includes a clock oscillator, a phase adjuster for adjusting the phase at each destination of the clock signal, an optical interconnection for supplying the clock signal to the phase adjuster, a reference signal generator for generating a phase reference signal from the clock signal, and an electrical interconnection for supplying the reference signal to the phase adjuster. The clock signal is supplied by an optical interconnection having a broad frequency bandwidth, and the phase reference signal by an electrical interconnection by which the skew is controlled easily. A clock signal adjusted to high phase accuracy can thus be distributed to following destinations by the phase adjuster.

Semiconductor device having an optical waveguide interposed in the space between electrode members

A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

Flip-flop circuit

An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block. The intra-block clock distribution circuitry in each of the blocks responds to the block-destined clock signal supplied to the associated block via one of the block-based clock signal wires connected thereto and the intra-block clock signals fed back via the feedback wires in the associated block to thereby generate a plurality of intra-block clock signals having respective phases which depend on differences in phase between the block-destined clock signal and the fed-back intra-block clock signals.

Intra-LSI clock distribution circuit

The present invention relates to a clock signal supplying device provided with an automatic phase regulating function for preventing errors in the phase regulation due to noise. In the device according to the present invention, there is disposed a reference signal serving as a phase reference, and transmission lines for clock signals and a transmission line for the reference signal are disposed from a clock signal supplying source to devices which are destinations of the distribution of clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. In the device, which is the destination of distribution of the clock signal, there is disposed a variable delay circuit for regulation of the phase of the clock signal and a phase comparing circuit for comparing the output of the variable delay circuit with the phase of the reference signal to output the result of the comparison. In the device according to the present invention, a noise filter is provided which detects phase regulation errors to effect correct phase regulation. Furthermore, the phase regulation is effected while avoiding a period of time wherein noise is apt to be produced.

Hiroyuki Itoh

Papers

Chip connection structure having diret through-hole connections through adhesive film and wiring substrate

Semiconductor device having an optical waveguide interposed in the space between electrode members

Flip-flop circuit

Intra-LSI clock distribution circuit

Clock signal supplying device having a phase compensation circuit