Al3O3 thin film growth on Si(100) using binary reaction sequence chemistry

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Design Of Integrated Circuits For Optical Communications

Trends in low-power circuit technologies of CMOS RAM chips are reviewed in terms of three key issues: charging capacitance, operating voltage, and dc current. The discussion includes a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs. In DRAMs, successive circuit advancements have produced a power reduction equivalent to two to three orders of magnitude over the last decade for a fixed memory capacity chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the major contributors to power reduction: lower charging capacitance due to partial activation of multi-divided arrays that use multi-divisions of data and word lines; and lower operating voltage resulting from external power supply reduction, half-V/sub DD/ precharging and on-chip voltage down converting scheme. In SRAMs, partial activation of a multi-divided word line drastically reduces the dc current from the data-line load to the selected cell. In addition to advances in the sense amplifier circuit, an auto power down scheme that uses address transition detection for word driver and column circuitry further reduces the dc current. It is also shown that to design ultralow voltage DRAMs and SRAMs, the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be indispensable in the future. >

Trends in low-power RAM circuit technologies

A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, and stored in the latch responsive to the clock signal. The digital signal stored in the latch is evaluated to determine if the stored digital signal has an expected value. The timing offset of the digital signal is thereafter adjusted relative to the clock signal. and the digital signal is once again stored in the latch responsive to the clock signal at the new timing offset. A number of digital signals at respective timing offsets relative to the clock signal are stored and evaluated, and a final timing offset of the digital signal is selected from the ones of the timing offsets that cause the latch to store the digital signal having the expected value. The timing offset of the digital signal is thereafter adjusted to the selected final timing offset. A read synchronization circuit may adaptively adjust the timing offset of digital signals in this manner, and such a read synchronization circuit may be utilized in many types of integrated circuits, including packetized dynamic random access memories, memory systems including a memory controller and one or more such packetized dynamic random access memories, and in computer systems including a plurality of such packetized dynamic random access memories.

Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

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Defect tolerance in VLSI circuits: techniques and yield analysis

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

Flip-flop circuit

To address the two main challenges concerning the design of a transimpedance amplifier (TIA), namely, improving the sensitivity of the TIA without sacrificing bandwidth and suppressing inter-symbol interference (ISI) due to insertion loss, a 25 Gb/s optical receiver (RX) based on 65 nm CMOS technology, including a TIA and a PD operating at 1.3 μm wavelength, was developed. The key components of the TIA are a two-stage offset-cancelation scheme and a low-voltage output driver with peaking gain of 7.7 dB at 12.5 GHz. This driver performance is achieved by separating the equalizer function and output buffer of the driver. The TIA attains a sensitivity of -9.7 dBm (86- μApp) OMA and an eye opening of 65% at data rate of 25 Gb/s. The optical RX operates at 28 Gb/s with sensitivity of -8.2 dBm (121- μApp) OMA. Utilizing the CMOS TIA, an implemented VCSEL-based optical link operating at 850 nm wavelength achieves sensitivity of -7.3 dBm (98- μApp) OMA. Power consumption and power efficiency of the optical RX at data rate of 28 Gb/s are respectively 137.5 mW and 4.9 mW/Gb/s.

A 25-to-28 Gb/s High-Sensitivity ( $-$ 9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects

A 600V three-phase single chip inverter IC has been developed using a new SOI technology instead of conventional 500V Dielectric Isolation (DI) technology. In this new technology, 600V high voltage devices were materialized with a newly introduced poly-Si field plate and a multi diffusion region in order to reduce the electric field. A new IGBT accomplishes high current density with an on-resistance of 1.8Ωmm
 2
 by using a multi emitter structure and an n-type well layer that reduces JFET resistance between emitter channels. Moreover, a thin Si layer and universal contact structure for fast extraction of excess carriers contribute to low switching losses. The turn-off energy loss of the IGBT is 54% of that of a conventional one at 135°C. The developed inverter IC has a maximum output voltage of 600V and a maximum output current 1A. Compared to the conventional 500V IC, the operational power consumption is reduced from 2.6W to 2.3W.

600V single chip inverter IC with new SOI technology

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25- mu m phase-shift optical lithography, and its basic operations are verified. A 0.72- mu m/sup 2/ double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 mu A and an access time of 48 ns. >

Hiroki Yamashita

Papers

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

Flip-flop circuit

A 25-to-28 Gb/s High-Sensitivity ( $-$ 9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects

600V single chip inverter IC with new SOI technology

256-Mb DRAM circuit technologies for file applications