An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

An electro-optical device having a plurality of pixels including a plurality of EL elements, wherein the electro-optical device provides a gray scale display by controlling a period of time at which the plurality of the EL elements emit light in one frame period; the plurality of the EL elements have a first electrode and a second electrode; the first electrode is held at a constant potential; and a potential of the second electrode changes in such a manner that a polarity of an EL driving voltage, which is a difference between the potentials applied to the first and second electrodes, is inverted for each one frame period.

Electro-optical device

Circuit modules and methods of construction thereof that contain composite meta-material dielectric bodies that have high effective values of real permittivity but which minimize reflective losses, through the use of host dielectric (organic or ceramic), materials having relative permittivities substantially less than ceramic dielectric inclusions embedded therein. The composite meta-material bodies permit reductions in physical lengths of electrically conducting elements such as antenna element(s) without adversely impacting radiation efficiency. The meta-material structure may additionally provide frequency band filtering functions that would normally be provided by other components typically found in an RF front-end.

Ceramic antenna module and methods of manufacture thereof

An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same

A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.

Method of fabricating a semiconductor device having a capacitor in a stacked memory cell

A fabrication method for a semiconductor integrated circuits which permits the self-aligned formation of contact windows without causing shorts or breaks in the interconnecting lines in the device is provided. After forming gate electrodes and source/drain regions of transistors on a semiconductor substrate, an etch-stop layer and a BPSG film are successively deposited over the gate electrodes and the source/drain regions. After a resist having a contact window pattern is formed on the BPSG film, an isotropic dry etching using a microwave plasma is performed to etch the BPSG film. According to the isotropic dry etching, the laterally etching rate in the BPSG film can be controlled by adjusting the RF power, and a silicon dioxide film can be used as the etch stop layer. After the BPSG flow process, the etch stop layer on the contact region is etched away to form contact windows.

Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window

A method is provided for producing a semiconductor device characterized by filling hollows having a high aspect ratio with a semiconductor film doped with impurities as dopants and an undoped semiconductor film, given that the doped polycrystalline Si film produced by thermal decomposition of reactive gases mixed with impurity gases and the undoped polycrystalline Si film produced by thermal decomposition of reactive gases containing no impurity gas have different step coverage characteristics from each other. The method allows uniform distribution of dopants as well as improvement of processing throughput by forming sequentially the two types of semiconductor films in one reaction chamber.

Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon

A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level

A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

Hisashi Ogawa

Papers

Method of fabricating a semiconductor device having a capacitor in a stacked memory cell

Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window

Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon

Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level

Method of fabricating a semiconductor device