Efficient switched network multicasting techniques are provided. Incoming multicast packets are processed by a central forwarding engine (CFE) in a network switch to generate forwarding indices used to make forwarding decisions for the packets based upon whether the packets are special multicast control packets or data packets. Forwarding of the special multicast control packets is determined by the switch's network management processor (NMP), while data packets are forwarded based upon conventional bridge forwarding techniques.

Efficient network multicast switching apparatus and methods

A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.

Technique for preconditioning I/Os during reconfiguration

A large flat IP network is created in a switched layer-2 network by adjusting the subnet masks of hosts such that these hosts can communicate directly with other hosts without the use of an intermediate router. The layer-2 switches are configured with user-selected IP subnets and monitor and analyze multicast packets to learn the mapping between IP subnets and switch ports. The layer-2 switches selectively forward the mulitcast packets based on the learned mappings between IP subnets and ports. After the destination host responds to the forwarded multicast, a direct connection is established between the source and destination hosts using the media access control addresses of both hosts.

Method and system for subnetting in a switched IP network

A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node having a home system memory. The remote node includes a local interconnect, a processing unit and at least one cache coupled to the local interconnect, and a node controller coupled between the local interconnect and the node interconnect. The processing unit first issues, on the local interconnect, a read-type request targeting data resident in the home system memory with a flag in the read-type request set to a first state to indicate only local servicing of the read-type request. In response to inability to service the read-type request locally in the remote node, the processing unit reissues the read-type request with the flag set to a second state to instruct the node controller to transmit the read-type request to the home node. The node controller, which includes a plurality of queues, preferably does not queue the read-type request until receipt of the reissued read-type request with the flag set to the second state.

Two-stage request protocol for accessing remote memory data in a NUMA data processing system

A simple mixed first level cache memory system (50) includes a level 1 cache (52) connected to a processor (54)by read data and write data lines (56) and (58). The level 1 cache (52) is connected to level 2 cache (60) by swap tag lines (62) and (64), swap data lines (66) and (68), multiplexer (70) and swap/read Line (72). The level 2 cache (60) is connected to the next lower level in the memorv hierarchy by write tag and write data lines (74) and (76). The next lower level in the memory hierarchy below the level 2 cache (60) is also connected by a read data line (78) through the multiplexer (70) and the swap/read line (72) to the level 1 cache (52). When processor (54) requires an instruction or data, it puts out an address on lines (80). If the instruction or data is present in the level 1 cache (52), it is supplied to the processor (54) on read data line (56). If the instruction or data is not present in the level 1 cache (52), the processor looks for it in the level 2 cache (60) by putting out the address of the instruction or data on lines (80). If the instruction or data is in the level 2 cache, it is supplied to the processor (54) through the level 1 cache (52) by means of a swap operation on tag swap lines (62) and (64), swap data lines (66) and (68), multiplexer (70) and swap/read data line (72). If the instruction or data is present in neither the level 1 cache (52) nor the level 2 cache (60), the address on lines (80) fetches the instruction or data from successively lower levels in the memory hierarchy as required via read data line (78), multiplexer (70) and swap/read data line (72). The instruction or data is then supplied from the level 1 cache to the processor (54).

System and method for exclusive two-level caching

A microprocessor capable of being incorporated in an information processing system with a cache memory unit and capable of realizing fine cache bypass control. The microprocessor can detect data to be cache-bypassed without checking bus status signals. The microprocessor is equipped with a cache bypass signal generator. Upon detection of data to be bypassed, the cache bypass signal generator generates a cache bypass request signal, which prevents the cache memory from performing a data caching operation on the data.

Microprocessor having cache bypass signal terminal

An integer division circuit performs a division operation on a dividend and a divisor each accomplished with sign information. The circuit includes a first latch circuit for temporarily storing, as sign control data, exclusive-OR operation data of the sign information of the dividend and divisor, an operation unit for forming a division operation on absolute value data of the dividend and divisor to produce a quotient, a correction circuit for correcting a sign of the quotient in response to the sign control data, and an overflow detection circuit for performing an exclusive-OR operation on the corrected-sign of the quotient and the sign control data to produce an overflow detection signal.

Integer division circuit provided with a overflow detector circuit

A data processing system comprises: an instruction queue memory; an instruction decode unit; an address computation unit; an address translation unit; and an instruction execution unit. Further comprised is a decoded instruction queue memory having a queue structure composed of a plurality of entries for latching an entry information. The decoded instruction queue memory includes: a first counter adapted to be counted up in response to the effective address computation requiring signal of the instruction decode unit and down in response to the translation completion signal of the address translation unit; and a second counter having a counting-down function. When the first and second counters are to be counted down, one closer to the instruction execution unit and having a counted value other than zero is counted down. When the queue is the decoded instruction queue memory advances, the first counter has its counted value copied to that of the second counter and then set at the value of zero. The instruction decode unit can execute the instruction decoding and execution in parallel, and a decoding, an effective address computation and an address translation of the decoded instruction in parallel, thereby to shorten the decoding time period.

Virtual memory arrangement data processing system with decoding and execution of prefetched instructions in parallel

An object of the present invention is to reduce the number of external connection terminals of an LSI that are required for performing testing in an operating state. The test signal output circuit of the present invention comprises one or more test signal output terminals, one or more test mode signal input terminals, a decoder for interpreting signals from the test mode signal input terminals, and one or more selectors for selecting internal signals in response to the output of the decoder and outputting the selected signals from the respective test signal output terminal.

Test signal output circuit for LSI

A data processor for executing an instruction designating a half-word length operation or a quarter-­word length operation in addition to one-word length operation is disclosed. This processor includes an operation unit performing an operation on data applied thereto and producing result data, a blocking register temporarily storing more significant bits data of a destination register, a first output circuit outputting less significant bits data of the result data when the half-word length operation or the quarter-word length operation is designated, and second output circuit operatively outputting the data of the blocking register. The outputs of the first and second circuits are then combined and written into the destination area.

Hitoshi Yamahata

Papers

Microprocessor having cache bypass signal terminal

Integer division circuit provided with a overflow detector circuit

Virtual memory arrangement data processing system with decoding and execution of prefetched instructions in parallel

Test signal output circuit for LSI

Data processor performing operation on data having length shorter than one-word length