Patent
Microprocessor having cache bypass signal terminal
Reads0
Chats0
TLDR
In this paper, a cache bypass signal generator is used to prevent the cache memory from performing a data caching operation on the data in order to prevent data to be cache-bypassed without checking bus status signals.Abstract:
A microprocessor capable of being incorporated in an information processing system with a cache memory unit and capable of realizing fine cache bypass control. The microprocessor can detect data to be cache-bypassed without checking bus status signals. The microprocessor is equipped with a cache bypass signal generator. Upon detection of data to be bypassed, the cache bypass signal generator generates a cache bypass request signal, which prevents the cache memory from performing a data caching operation on the data.read more
Citations
More filters
Patent
Efficient network multicast switching apparatus and methods
TL;DR: In this article, a central forwarding engine (CFE) is used in a network switch to generate forwarding indices used to make forwarding decisions for the packets based upon whether the packets are special multicast control packets or data packets.
Patent
Method and system for subnetting in a switched IP network
TL;DR: In this paper, a flat IP network is created in a switched layer-2 network by adjusting the subnet masks of hosts such that these hosts can communicate directly with other hosts without the use of an intermediate router.
Patent
Two-stage request protocol for accessing remote memory data in a NUMA data processing system
TL;DR: In this paper, a read-type request targeting data resident in the home system memory with a flag in the readtype request set to a first state to indicate only local servicing of the read type request is made.
Patent
System and method for exclusive two-level caching
TL;DR: A simple mixed first level cache memory system as mentioned in this paper includes a level 1 cache (52) connected to a processor (54) by read data and write data lines (56) and (58).
Patent
Method and apparatus for selective data caching implemented with noncacheable and cacheable data for improved cache performance in a computer networking system
TL;DR: In this article, the cache controller determines whether the requested data object is to be cached or is exempt from being cached, and then it is loaded directly into a local memory and is not stored in the cache.
References
More filters
Patent
Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
TL;DR: Partition Look-Aside Table (PLAT) as discussed by the authors is a cache partition identifier, a control field, and a congruence-class address for locating associated data in the identified partition.
Patent
Input/output cache system including bypass capability
Jaime Calle,Lawrence W Chelberg +1 more
TL;DR: In this paper, a local memory of an input/output system includes a cache store and a backing store, and each memory command applied to the memory unit incudes a predetermined bit which is coded to designate when the information requested from the local memory unit is to be written into the cache store.
Patent
Write-shared cache circuit for multiprocessor system
TL;DR: A write-shared cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system as mentioned in this paper.
Patent
Cache store bypass for computer
TL;DR: In this article, an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), and vector processing units (148, 150).
Patent
Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction
TL;DR: In this article, the cache memory control circuit detects whether access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to write onto, the particular region, the data are copied onto the cache, and operation of memory is executed immediately without waiting for the reference of cache memory.