interpretation is a technique for the static detection of dynamic properties of programs. It is semantics based, that is, it computes approximative properties of the semantics of programs. On this basis, it supports correctness proofs of analyses. It replaces commonly used ad hoc techniques by systematic, provable ones, and it allows for the automatic generation of analyzers from specifications by existing tools. In this work, abstract interpretation is applied to the problem of predicting the cache behavior of programs. semantics of machine programs are defined which determine the contents of caches. For interprocedural analysis, existing methods are examined and a new approach that is especially tailored for the cache analysis is presented. This allows for a static classification of the cache behavior of memory references of programs. The calculated information can be used to improve worst case execution time estimations. It is possible to analyze instruction, data, and combined instruction/data caches for common (re)placement and write strategies. Experimental results are presented that demonstrate the applicability of the analyses.

Efficient and Precise Cache Behavior Prediction for Real-TimeSystems

The question whether preemptive algorithms are better than nonpreemptive ones for scheduling a set of real-time tasks has been debated for a long time in the research community. In fact, especially under fixed priority systems, each approach has advantages and disadvantages, and no one dominates the other when both predictability and efficiency have to be taken into account in the system design. Recently, limited preemption models have been proposed as a viable alternative between the two extreme cases of fully preemptive and nonpreemptive scheduling. This paper presents a survey of the existing approaches for reducing preemptions and compares them under different metrics, providing both qualitative and quantitative performance evaluations.

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Limited Preemptive Scheduling for Real-Time Systems. A Survey

Cache memories have been extensively used to bridge the gap between high speed processors and relatively slow main memories However, they are a source of predictability problems because of their dynamic and adaptive behavior and thus need special attention to be used in hard-real time systems A lot of progress has been achieved in the last ten years to statically predict the worst-case behavior of applications with respect to caches in order to determine safe and precise bounds on task worst-case execution times (WCETs) and cache-related preemption delays An alternative approach to cope with caches in real-time systems is to statically lock their contents such that memory access times and cache-related preemption times are predictable In this paper, we propose two low-complexity algorithms for selecting the contents of statically-locked caches We evaluate their performances and compare them with those of a state of the art static cache analysis method

Low-complexity algorithms for static cache locking in multitasking hard real-time systems

Compared to software development for desktop systems, curr ent software design practice for embedded systems is still archaic. C/C++ and ev en assembler are used on top of a small real-time operating system. Many of the benefit s of Java, such as safe object references, the notion of concurrency as a first-clas s language construct, and its portability, have the potential to make embedded system much safer and simpler to program. However, Java technology is seldom used in embed ded systems, due to the lack of acceptable real-time performance. This thesis presents a Java processor designed for time-pre dictable execution of real-time tasks. JOP (Java Optimized Processor) is the impl e entation of the Java virtual machine in hardware. JOP is intended for applicatio ns in embedded real-time systems and the primary implementation technology is in a fie ld programmable gate array. This research demonstrates that a hardware implemen tation of the Java virtual machine results in a small design for resource-constrained devices. Architectural advancements in modern processor designs in crease average performance with features such as pipelines, caches and branch pre diction. However, these features complicate worst-case execution time (WCET) anal ysis and lead to very conservative WCET estimates. This thesis tackles this prob lem from the architectural perspective – by introducing a processor architectur in which simpler and more accurate WCET analysis is more important than average case p erformance. This thesis evaluates the issues surrounding the use of stan dard Java for real-time applications. In order to overcome some of the issues with st andard Java, a profile for real-time Java is defined. Tight integration of the realtime scheduler with the supporting processor result in an efficient platform for Jav a in embedded real-time systems. The proposed processor and the Java real-time profile have be en us d with success to implement several commercial real-time applications.

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JOP: A Java Optimized Processor for Embedded Real-Time Systems

Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multiprocessing, a popular approach for performance enhancement, opens up the opportunity for concurrent execution. However due to contention for any shared memory by different processing cores, memory access behavior becomes more unpredictable, and hence harder to analyze. In this paper, we develop a timing analysis method for concurrent software running on multi-cores with a shared instruction cache. Communication across tasks is by message passing. Our method progressively improves the lifetime estimates of tasks that execute concurrently on multiple cores, in order to estimate potential conflicts in the shared cache. Possible conflicts arising from overlapping task lifetimes are accounted for in the hit-miss classification of accesses to the shared cache, to provide safe execution time bounds. We show that our method produces lower worst-case response time (WCRT) estimates than existing shared-cache analysis on a real-world embedded application. Furthermore, we also exploit instruction cache locking to improve WCRT. By locking some beneficial memory blocks into L1 cache, the WCET of the tasks and L2 cache conflicts are reduced, resulting in better WCRT. Experiments demonstrate that significant WCRT reduction is achieved through cache locking.

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Timing analysis of concurrent programs running on shared cache multi-cores

We propose a technique for analyzing cache-related preemption delays of tasks that cause unpredictable variation in task execution time in the context of fixed-priority preemptive scheduling. The proposed technique consists of two steps. The first step performs a per-task analysis to estimate cache-related preemption cost for each execution point in a given task. The second step computes the worst case response time of each task that includes the cache-related preemption delay using a response time equation and a linear programming technique. This step takes as its input the preemption cost information of tasks obtained in the first step. This paper also compares the proposed approach with previous approaches. The results show that the proposed approach gives a prediction of the worst case cache-related preemption delay that is up to 60 percent tighter than those obtained from the previous approaches.

Hoosun Hahn

Papers

Analysis of cache-related preemption delay in fixed-priority preemptive scheduling