As in other computer architecture areas, interconnection networks research relies most of the times on simulation tools. This paper announces the release of an open-source tool suitable to be used for accurate modeling from small CMP to large supercomputer interconnection networks. The cycle-accurate modeling of TOPAZ can be used standalone through synthetic traffic patterns and application-traces or within full-system evaluation systems such as GEMS or GEM5 effortlessly. In fact, we provide an advanced interface that enables the replacement of the original lightweight but optimistic GEMS and GEM5 network simulator with limited performance impact on the simulation time. Our tests indicate that in this context, underestimating network modeling could induce up to 50% error in the performance estimation of the simulated system. To minimize the impact of detailed network modeling on simulation time, we incorporate mechanisms able to attenuate the higher computational effort, reducing in this way the slowdown of the full system simulation with accurate performance estimations. Additionally, in order to evaluate large-scale networks, we parallelize the simulator to be able to optimize memory resources with the growing number of cores available per chip in the simulation farms. This allows us to simulate node networks exceeding one million of routers with up to 70% efficiency in a multithreaded simulation running on twelve cores.

/pdf/topaz-an-open-source-interconnection-network-simulator-for-266uccp854.pdf

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers

On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and power budgets. While running a traffic trace, however, not all input ports of routers have incoming packets needed to be transferred simultaneously. Therefore, a large number of buffer queues in the network are empty and other queues are mostly busy. This observation motivates us to design router architecture with shared queues (RoShaQ), router architecture that maximizes buffer utilization by allowing the sharing multiple buffer queues among input ports. Sharing queues, in fact, makes using buffers more efficient hence is able to achieve higher throughput when the network load becomes heavy. On the other side, at light traffic load, our router achieves low latency by allowing packets to effectively bypass these shared queues. Experimental results on a 65-nm CMOS standard-cell process show that over synthetic traffics RoShaQ has 17% less latency and 18% higher saturation throughput than a typical virtualchannel (VC) router. Because of its higher performance, RoShaQ consumes 9% less energy per transferred packet than VC router given the same buffer space capacity. Over real multitask applications and E3S embedded benchmarks using near-optimal NMAP mapping algorithm, RoShaQ has 32% lower latency than VC router and targeting the same application throughput with 30% lower energy per packet.

Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Introduction System-on-Chip Integration and Its Challenges SoC to Network-on-Chip: A Paradigm Shift Research Issues in NoC Development Existing NoC Examples Summary References Interconnection Networks in Network-on-Chip Introduction Network Topologies Switching Techniques Routing Strategies Flow Control Protocol Quality-of-Service Support NI Module Summary References Architecture Design of Network-on-Chip Introduction Switching Techniques and Packet Format Asynchronous FIFO Design GALS Style of Communication Wormhole Router Architecture Design VC Router Architecture Design Adaptive Router Architecture Design Summary References Evaluation of Network-on-Chip Architectures Evaluation Methodologies of NoC Traffic Modeling Selection of Channel Width and Flit Size Simulation Results and Analysis of MoT Network with WH Router Impact of FIFO Size and Placement in Energy and Performance of a Network Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic Simulation Results and Analysis of MoT Network with Virtual Channel Router Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router Limitations of Tree-Based Topologies Summary References Application Mapping on Network-on-Chip Introduction Mapping Problem ILP Formulation Constructive Heuristics for Application Mapping Constructive Heuristics with Iterative Improvement Mapping Using Discrete PSO Summary References Low-Power Techniques for Network-on-Chip Introduction Standard Low-Power Methods for NoC Routers Standard Low-Power Methods for NoC Links System-Level Power Reduction Summary References Signal Integrity and Reliability of Network-on-Chip Introduction Sources of Faults in NoC Fabric Permanent Fault Controlling Techniques Transient Fault Controlling Techniques Unified Coding Framework Energy and Reliability Trade-Off in Coding Technique Summary References Testing of Network-on- Chip Architectures Introduction Testing Communication Fabric Testing Cores Summary References Application-Specific Network-on-Chip Synthesis Introduction ASNoC Synthesis Problem Literature Survey System-Level Floorplanning Custom Interconnection Topology and Route Generation ASNoC Synthesis with Flexible Router Placement Summary References Reconfigurable Network-on-Chip Design Introduction Literature Review Local Reconfiguration Approach Topology Reconfiguration Link Reconfiguration Summary References Three-Dimensional Integration of Network-on-Chip Introduction 3-D Integration: Pros and Cons Design and Evaluation of 3-D NoC Architecture Summary References Conclusions and Future Trends Conclusions Future Trends Comparison between Alternatives References Index

Network-on-Chip: The Next Generation of System-on-Chip Integration

In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm which can enhance the NoC communication performance with minimal energy overhead. In particular, our proposed NoC architecture exploits the following two features: i) self-reconfigurable bidirectional channels to increase the effective bandwidth and ii) express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. A deadlock-free and traffic-aware dynamic routing algorithm is further developed for the proposed architecture, which can take advantage of the increased flexibility in the proposed architecture. Both the channels self-reconfiguration and routing decisions are made in a distributed fashion, based on a function of the localized traffic conditions, in order to maximize the performance and minimize the energy costs at the macroscopic level. Our simulation results show that the proposed approach can reduce the network latency by 30\% -80\% in most cases compared to a conventional unidirectional mesh topology, while incurring less than 15\% power overhead.

A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture

A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow. This area-efficient BiNoC router delivers better performance and requires smaller buffer size than that of a conventional network-on-chip (NoC). The flow direction at each channel is controlled by a channel direction control (CDC) algorithm. Implemented with a pair of finite state machines, this CDC algorithm is shown to be high performance, free of deadlock, and free of starvation. Extensive cycle-accurate simulations using synthetic and real-world traffic patterns have been conducted to evaluate the performance of the BiNoC. These results exhibit consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.

Hsiao-An Lin

Papers

A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel