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Journal ArticleDOI

A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel

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TLDR
Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow and exhibits consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.
Abstract
A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow. This area-efficient BiNoC router delivers better performance and requires smaller buffer size than that of a conventional network-on-chip (NoC). The flow direction at each channel is controlled by a channel direction control (CDC) algorithm. Implemented with a pair of finite state machines, this CDC algorithm is shown to be high performance, free of deadlock, and free of starvation. Extensive cycle-accurate simulations using synthetic and real-world traffic patterns have been conducted to evaluate the performance of the BiNoC. These results exhibit consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.

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Citations
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Proceedings ArticleDOI

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers

TL;DR: The release of an open-source tool suitable to be used for accurate modeling from small CMP to large supercomputer interconnection networks, and incorporates mechanisms able to attenuate the higher computational effort.
Journal ArticleDOI

Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

TL;DR: Over real multitask applications and E3S embedded benchmarks using near-optimal NMAP mapping algorithm, RoShaQ has 32% lower latency than VC router and targeting the same application throughput with 30% lower energy per packet.
Journal ArticleDOI

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

TL;DR: A router design supporting best effort and connection-oriented guaranteed service communication for simultaneous guaranteed service Communication flows is presented and an algorithm is presented that is used to establish guaranteed service connections according to the applications bandwidth requirements.
Book

Network-on-Chip: The Next Generation of System-on-Chip Integration

TL;DR: System-on-Chip Integration and Its Challenges SoC to Network-on -Chip: A Paradigm Shift Research Issues in NoC Development Existing NoC Examples Summary References Interconnection Networks in Network- on-Chip Introduction Network Topologies Switching Techniques Routing Strategies Flow Control Protocol Quality-of-Service Support NI Module Summary References Architecture Design of Network- On-Chip.
Proceedings ArticleDOI

A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture

TL;DR: Simulation results show that the proposed approach can reduce the network latency by 30\% -80\% in most cases compared to a conventional unidirectional mesh topology, while incurring less than 15\% power overhead.
References
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Journal ArticleDOI

Networks on chips: a new SoC paradigm

TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Book

Principles and Practices of Interconnection Networks

TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
Proceedings ArticleDOI

Route packets, not wires: on-chip interconnection networks

TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Journal ArticleDOI

A survey of research and practices of Network-on-chip

TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Journal ArticleDOI

The future of wires

TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.