A single error correcting double error detecting (SEC/DED) error correcting code for a memory is used to correct one fixed error and one transitory error in a data word stored in the memory. The erroneous data word and syndrome generated therefrom by the error correcting code circuitry are saved while the memory location of the flawed word is checked to determine the location of the one fixed error using a ancillatory error correction technique. A syndrome is then generated for the word assuming only a single fixed error in the location determined using the ancillatory technique. Thereafter, the generated and saved syndromes are exclusive OR'd together to obtain another syndrome locating the position of the transitory error. With both errors located, the word is corrected by inverting the erroneous data bits.

Double error correction using single error correcting code

Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.

Error logging memory system for avoiding miscorrection of triple errors

A paging receiver (25) receiving message information having one of a plurality of (BCH) code word structures has a programmable error correcting apparatus (32) for correcting bit errors within the message information. The programmable error correcting apparatus (32) may be configured in response to identifying a signalling system and the code word structure corresponding to the signalling system, or in response to changes in the code word structure within the message. A simplified error correcting apparatus may correct a single bit error within a code word structure. The programmable error correcting apparatus (32) is capable of correcting any two bit error combination within the code word structure and contains sequential and combinational logic circuits. The programmable error correcting apparatus is integrated together with a microprocessor on a monolithic integrated circuit.

Programmable error correcting apparatus within a paging receiver

An error detection and correction method and apparatus is described which permits the correction of double errors using a (15,11) Hamming code and a parity bit. The Hamming code and parity bit allows the detection of double errors. A modulated waveform carrying the binary data is examined for anomalies such as noise pulses. A hint signal is generated based on the anomalies which points to a suspect bit. The state of this bit is changed to correct for double errors.

Binary data error correction using hint signal

A method for correcting errors in up to three tracks or channels in a multi-track data system is provided. Message data is formed into a codeword by adding three check bytes thereto which are dependent on each other and are generated from the information bytes. After the data has undergone some form of transposition, at which time it is desirable to check for errors and correct any errors within the capability of the code, the transposed data is decoded so as to generate three syndromes. At the time of data transposition, error pointers may be provided. When the provided pointers indicate that either two or three tracks contain errors, error patterns are generated and added to the information already within the tracks in error, to correct the errors. If only one pointer is provided, a check is made to see whether or not another track is in error even though a pointer was not provided, and, if an additional track is in error, its pointer is generated. Thereafter these two tracks are corrected. Similarly, if no pointer is provided, a check is made to determine whether or not there was at least one track in error. If so, the pointer is generated and the error is corrected. An uncorrectable error indication is provided when errors are encountered that lie outside of the correction capability of the code.

Triple track error correction

A method and apparatus are provided for detecting and correcting double errors automatically by generating syndrome S bits from a binary word having check bits and data bits. The syndrome S bits themselves are decoded to locate and correct single errors. Wen double errors occur in the binary word, the syndrome S bits automatically operate a switching device which changes the bits of the binary word one at a time to correct one of the double errors. If one of the double errors is not corrected when a given bit is changed, this is indicated by the syndrome S bits, and the bit under test is restored as the next bit of the binary word is changed or complemented. Whenever one of the double errors is corrected by the switching device, the syndrome bits then indicate the location of the remaining single error, and the syndrome S bits are decoded to correct the second one of the double errors.

Hsiao Mu-Yue

Papers

Automatic double error detection and correction apparatus