A thorough analysis of the FinFET resistance and current distribution is presented. By combining multiple conventional and novel measurement techniques, the key components that contribute to the parasitic resistance of FinFETs can be quantified. Through a three-dimensional (3D) FinFET resistance network model, the impact of the FinFET 3D structure on the current distribution and parasitic resistance is analyzed. The heterogeneous current distribution, known as the current crowding effect, is also discussed with possible alleviation methods through 3D simulation.

https://iopscience.iop.org/article/10.7567/JJAP.55.04ED16/pdf

Effect of three-dimensional current distribution on characterizing parasitic resistance of FinFETs

A DTM Research based on the strategic process

In this work a 22nm Dual Gate Enhancement Mode Junction Field Effect Transistor (DG-JFET) structure is proposed and its behavior as a MOS capacitor is studied. The results have shown that, the proposed DG-JFET has better short channel effect (SCE) suppression and a lower threshold voltage than MOSFETs. DG-JFETs were recognized as one of the possible choice to continue the scaling beyond the conventional limits. DAVINCI (a Synopsys® 3D-device simulation tool) is used to analyze the device architecture and performance initially. The numerical device simulation results show that the enhancement mode DG-JFETs as an emerging technology to extend the scaling and the parasitic behavior of the device is analyzed from the carrier profile.

DG-JFET for Low Power Applications and Behavior of It as a MOS Capacitor

In this paper, we propose a hybrid refinement approach to improve the accuracy of static analysis. It keeps condition constraints information during forward dataflow analysis and gets the satisfiability of a warning by a constraint solver taking as input such information and path conditions; data regression analysis can remedy the capability of handling loops and library calls of abstract interpretation technique. It has been implemented in our static analysis tool, Defect Testing System (DTS) and deployed on a internetware environment TRUSTIE. Experiment on a large number of C open source projects shows the great improvement this strategy makes.

A hybrid static analysis refinement approach within internetware environment

The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

HU Chenming

Papers

Scaling CMOS devices through alternative structures