Journal ArticleDOI
Scaling CMOS devices through alternative structures
TLDR
It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times, that is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years.Abstract:
The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.read more
Citations
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Journal ArticleDOI
Effect of three-dimensional current distribution on characterizing parasitic resistance of FinFETs
TL;DR: In this paper, a thorough analysis of the FinFET resistance and current distribution is presented by combining multiple conventional and novel measurement techniques, and the key components that contribute to the parasitic resistance of Fin-FETs can be quantified.
Journal ArticleDOI
A DTM Research based on the strategic process
TL;DR: The host guiding mobile agent shielding technology is sorted out, a technique to intensify the reliability shield of mobile representative (named as IEOP procedure) is proposed, and this method can block most malicious attacks on mobile agents, and can protect the integrity and confidentiality of mobile agents.
Proceedings ArticleDOI
DG-JFET for Low Power Applications and Behavior of It as a MOS Capacitor
TL;DR: In this paper, a 22nm dual gate enhancement mode junction field effect transistor (DG-JFET) structure is proposed and its behavior as a MOS capacitor is studied.
Proceedings ArticleDOI
A hybrid static analysis refinement approach within internetware environment
TL;DR: A hybrid refinement approach to improve the accuracy of static analysis that keeps condition constraints information during forward dataflow analysis and gets the satisfiability of a warning by a constraint solver taking as input such information and path conditions.
References
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Proceedings ArticleDOI
A folded-channel MOSFET for deep-sub-tenth micron era
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,E. Anderson,Hideki Takeuchi,K. Asano,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a quasi-planar fold-channel transistor structure was proposed for the vertical double-gate SOI MOSFETs, which improved the short channel effect immunities.
Proceedings ArticleDOI
A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET
TL;DR: A fully depleted lean channel transistor (DELTA) with a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported in this paper.
Journal ArticleDOI
Future CMOS scaling and reliability
TL;DR: In this paper, the authors reviewed the goals and constraints of MOSFET scaling and highlighted the role of reliability constraints, and concluded that judicial shrinking of device dimensions can sustain the historical trend of scaling through the 0.09-mu m (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010.
Journal ArticleDOI
Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
TL;DR: In this paper, a 40nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide.
Proceedings ArticleDOI
A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs
Kazumasa Sunouchi,Hiroshi Takato,Naoko Okabe,Takashi Yamada,Tohru Ozaki,S. Inoue,Kazuhiko Hashimoto,Katsuhiko Hieda,Akihiro Nitayama,Fumio Horiguchi,F. Masuoka +10 more
TL;DR: In this paper, a novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs).