A system, method, and software product in a computer aided design apparatus for system design, to simultaneously optimize multiple performance criteria models of the system, where the performance criteria models are characterized by convex cost functions based on linear dimensional characteristics of system being designed. One embodiment is provided in a computer aid design environment for integrated circuit design, and used to simultaneously optimize fabrication yield along with other performance criteria. Optimization is provided by converting a structural description of an integrated circuit into a constraint graph, compacting, and modifying the constraint graph to include convex cost functions for selected performance criteria to optimized, such as yield cost functions. The cost functions are then transformed to piecewise linear cost functions. The constraint graph is then expanded by replacing edges having piecewise linear cost function with subgraphs constructed from the piecewise linear cost function. The expanded constraint graph is then minimized using a network flow algorithm. Once minimized, the constraint graph describes the positions of circuit elements that maximize yield (and other selected performance criteria) given the cost functions.

Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions

Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec$cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.

Analyzing the effectiveness of multiple-detect test sets

A system, method, and software product in a computer aided design apparatus for system design, to simultaneously optimize multiple performance criteria models of the system, where the performance criteria models are characterized by convex cost functions based on linear dimensional characteristics of the system being designed. One embodiment is provided in a computer aid design environment for integrated circuit design, and used to simultaneously optimize fabrication yield along with other performance criteria. Optimization is provided by converting a structural description of an integrated circuit into a constraint graph, compacting, and modifying the constraint graph to include convex cost functions for selected performance criteria to be optimized, such as yield cost functions. The cost functions are then transformed to piecewise linear cost functions. The constraint graph is directly minimized by an improved wire length minimizer that treats the piecewise linear cost function of each edge of the constraint graph as if it were a subgraph, without actually expanding the constraint graph with the subgraphs of the piecewise linear cost functions. Once minimized, the constraint graph describes the positions of circuit elements that maximize yield (and other selected performance criteria) given the cost functions.

Optimization multiple performance criteria by simulating the behavior of a constraint graph expanded by subgraphs derived from PWL convex cost functions

Escalating demand for mixed-signal Integrated Circuits has been accompanied by the need to develop efficient strategies to guarantee higher quality at lower cost. One key to achieving this is efficient production test and the utilization of Design-for-Testability (DfT). Fault simulation based test evaluation would be a major contribution towards measuring and optimizing the effectiveness of a production test. Fault simulations, however, are only useful if the underlying fault list generation approaches accurately reflect manufacturing defects-both in their probability of occurrence and in their electrical behavior. This paper evaluates and compares two fault list generation approaches and the implications on test optimization. Fault lists derived from both Inductive Fault Analysis (IFA) and a transistor fault-model are compared for a testability analysis on a self-test function for a high-performance switched-current design.

Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

The electrical behavior of a floating gate MOS transistor is mask-topology-dependent, i.e. floating on different sites of interconnection may result in different fault behavior. In this paper, we present a net-oriented deterministic approach to compute the probability of different open faults on each net, by taking into account the process defect statistics and mask layout data. The open faults causing floating gates are classified into three types, i.e. (1) open causes floating gates of p-channel transistors, (2) open causes floating gates of n-channel transistors, and (3) open causes floating gates of both p-channel transistors and n-channel transistors. For each net the probabilities of floating gate faults (1), (2) and (3) are obtained. The results of the analysis can be used as guidelines for designing more reliable and testable circuits, adopting more accurate fault models, introducing effective testing strategies. >

Probability analysis for CMOS floating gate faults

In this paper, a net-oriented method to analyze realistic faults is presented. The key point of the method is to analyze the faults caused by a spot defect net by net. First the possible faults related to a net are extracted. Hence all faults in a layout are extracted by enumerating all nets on the layout. An approach to calculate the critical area with respect to each fault is also described. A formula is proposed to compute the fault weight theoretically instead of weighting a fault by counting the number of appearances of the fault. The proposed method has been implemented on a HP750 workstation. To demonstrate its practical performance, all layouts in iscas85 benchmarks as well as some other layouts ranging from 450 to 28,000 transistors have been analyzed. The results show that our method is much faster than other approaches published in literature.

A net-oriented method for realistic fault analysis

The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based on this analysis, a general routing cost function is presented, in which the manufacturability of a net is taken into account in conjunction with the traditional routing objectives. The new cost function, relating the process spot defects to the routing procedure has been implemented. For the benchmark layouts obtained by both the original routing tool and the new routing module, the failure probabilities are analyzed. The results show that the failure probability of a layout is significantly decreased if the spot defect mechanism is taken into account in the routing procedure, while the area of the layout is kept constant.

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Hua Xue

Papers

A net-oriented method for realistic fault analysis

Routing for Manufacturability