The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")Includes three review appendices in the printed text. Additional reference appendices are available online.Includes updated Case Studies and completely new exercises.

Computer Architecture, Fifth Edition: A Quantitative Approach

As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. We propose a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) that achieves substantially higher accuracy than any other scheme reported in the literature. The mechanism uses two levels of branch history information to make predictions, the history of the last k branches encountered, and the branch behavior for the last s occurrences of the specific pattern of these k branches. We have identified three variations of the Two-Level Adaptive Branch Prediction, depending on how finely we resolve the history information gathered. We compute the hardware costs of implementing each of the three variations, and use these costs in evaluating their relative effectiveness. We measure the branch prediction accuracy of the three variations of two-Level Adaptive Branch Prediction, along with several other popular proposed dynamic and static prediction schemes, on the SPEC benchmarks. We show that the average prediction accuracy for Two-Level Adaptive Branch Prediction is 97 percent, while the other known schemes achieve at most 94.4 percent average prediction accuracy. We measure the effectiveness of different prediction algorithms and different amounts of history and pattern information. We measure the costs of each variation to obtain the same prediction accuracy.

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Alternative implementations of two-level adaptive branch prediction

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACETM along with its companion Trace SchedulingTM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.

A VLIW architecture for a trace scheduling compiler

High-performance microarchitectures use, among other structures, deep pipelines to help speed up exe- cution. The importance of a good branch predictor to the effectiveness of a deep pipeline in the presence of condi- tional branches is well-known. In fact, the literature contains proposals for a number of branch prediction schemes. Some are static in that they use opcode information and profiling statistics to make predictions. Others are dynamic in that they use run-time execution history to make predictions. This paper proposes a new dynamic branch predictor, the Two-Level Adaptive Paining scheme, which alters the branch prediction algorithm on the basis of information collected at run-time. Several configurations of the Two-Level Adaptive Training Branch Predictor are introduced, simulated, and compared to simulations of other known static and dynamic branch prediction schemes. Two-Level Adaptive Training Branch Prediction achieves 97 percent accuracy on nine of the ten SPEC benchmarks, compared to less than 93 percent for other schemes. Since a prediction miss requires flushing of the speculative execution already in progress, the relevant metric is the miss rate. The miss rate is 3 percent for the Two-Level Adaptive Training scheme vs. 7 percent (best case) for the other schemes. This represents more than a 100 percent improvement in reducing the number of pipeline hushes required.

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Two-level adaptive training branch prediction

Traces are dynamic instruction sequences constructed and cached by hardware. A microarchitecture organized around traces is presented as a means for efficiently executing many instructions per cycle. Trace processors exploit both control flow and data flow hierarchy to overcome complexity and architectural limitations of conventional superscalar processors by (1) distributing execution resources based on trace boundaries and (2) applying control and data prediction at the trace level rather than individual branches or instructions. Three sets of experiments using the SPECInt95 benchmarks are presented. (i) A detailed evaluation of trace processor configurations: the results affirm that significant instruction-level parallelism can be exploited in integer programs (2 to 6 instructions per cycle). We also isolate the impact of distributed resources, and quantify the value of successively doubling the number of distributed elements. (ii) A trace processor with data prediction applied to inter-trace dependences: potential performance improvement with perfect prediction is around 45% for all benchmarks. With realistic prediction, gcc achieves an actual improvement of 10%. (iii) Evaluation of aggressive control flow: some benchmarks benefit from control independence by as much as 10%.

Trace processors

A new method of implementing branch instructions is presented. This technique has been implemented in the CRISP Microprocessor. With a combination of hardware and software techniques the execution time cost for many branches can be effectively reduced to zero. Branches are folded into other instructions, making their execution as separate instructions unnecessary. Branch Folding can reduce the apparent number of instructions needed to execute a program by the number of branches in that program, as well as reducing or eliminating pipeline breakage. Statistics are presented demonstrating the effectiveness of Branch Folding and associated techniques used in the CRISP Microprocessor.

Branch folding in the CRISP microprocessor: reducing branch delay to zero

The AT&T CRISP Microprocessor is a high performance general purpose 32-bit processor. It has been implemented as a single CMOS chip containing 172,163 transistors in a 1.75~t CMOS technology and runs at a clock frequency of 16 MHz. 1 The CRISP Microprocessor achieves performance through traditional techniques, such as pipelining, and from several new techniques not before found in microprocessor designs. This paper focuses on a detailed description of hardware architecture, including the pipeline structure and details of the architectural innovations. A brief introduction to the instruction-set and major features are given for background.

The hardware architecture of the CRISP microprocessor

A computer system arranged for faster processing operations by providing a stack cache in internal register memory. A full stack is provided in main memory. The stack cache provides a cache representation of part of the main memory stack. Stack relative addresses contained in procedure instructions are converted to absolute main memory stack addresses. A subset of the absolute main memory stack address is used to directly address the stack cache when a "hit" is detected. Otherwise, the main memory stack is addressed. The stack cache is implemented as a set of contiguously addressable registers. Two stack pointers are used to implement allocation space in the stack as a circulating buffer. Cache hits are detected by comparing the absolute stack address to the contents of the two circular buffer pointers. Space for a procedure is allocated upon entering a procedure. The amount of space to allocate is stored in the first instruction. Space is deallocated when a procedure is terminated. The deallocation space is stored in the first instruction executed after procedure termination.

Computer with automatic mapping of memory contents into machine registers during program execution

Since 1975 the Bell Labs C Machine Project has designed several computer architectures to support the C programming language1 efficiently. These designs have evolved into the current C Machine instruction set architecture. The CRISP Microprocessor is one particular implementation of that architecture. Since we wish to describe the capabilities of a particular implementation in this paper, we will use "CRISP" in describing both the architecture and the implementation. While C Machines are designed to execute the C programming language particularly well, this by no means excludes the efficient execution of other languages.2

Introduction to the CRISP Instruction Set Architecture.

The class of portable hybrid computer/communication devices called personal communicators requires a microprocessor that simultaneously maximizes performance and minimizes power dissipation and silicon real estate. AT&T's 92010 Hobbit microprocessor combines reduced instruction set computer (RISC) architectural features, some non-RISC features, and an innovative electrical implementation to exactly target the personal communicator application. The authors give an overview of the Hobbit architecture and implementation, and demonstrate how the design achieved superior performance and low power. At 20 MHz, the performance of Hobbit is 13.5 VAX MIPS and 27000 Dhrystones/s, with only 250 mW of power at 3.3 V and 900 mW at 5.0 V. The performance/power ratio of 54 VAX MIPS/W is significantly superior to that of conventional RISC and CISC microprocessors. >

Hubert R. McLellan

Papers

Branch folding in the CRISP microprocessor: reducing branch delay to zero

The hardware architecture of the CRISP microprocessor

Computer with automatic mapping of memory contents into machine registers during program execution

Introduction to the CRISP Instruction Set Architecture.

Hobbit: a high-performance, low-power microprocessor