In this paper, novel selective encryption image schemes based on JPEG2000 are proposed. The first one encrypts only the code-blocks corresponding to some sensitive precincts. In order to improve the security level we introduce the permutation of codeblocks contributing in the selected precincts. The idea of combining permutation and selective encryption is used in order to minimize the amount of processed data encryption while ensuring the best possible degradation through the permutation.

Many of proposals format compliant encryption schemes for JPEG2000 that have been made encrypt packet body data, but leave header packet in plaintext. The second approach, combines code-blocks data encryption to a cyclic permutation of all packets headers in the bitstream. Actually, in the JPEG2000 codestream, packet header information is specific to the visual content, and it is can be used as a fingerprint of the codestream.

Symmetric encryption AES with CFB mode is used to encrypt in the two schemes.

The proposed schemes don't introduce superfluous JPEG2000 markers in the protected codestream, i.e, its format is compliant to JPEG2000 codestream one. It keeps file format and compression ratio unchanged and doesn't degrade the original error robustness. The proposed scheme works with any standard ciphers and introduces negligible computational cost.

Selective encryption techniques of JPEG2000 codestream for medical images transmission

The latest video coding standard high-efficiency video coding (HEVC) provides 50% improvement in coding efficiency compared to H.264/AVC to meet the rising demands for video streaming, better video quality, and higher resolution. The deblocking filter (DF) and sample adaptive offset (SAO) play an important role in the HEVC encoder, and the SAO is newly adopted in HEVC. Due to the high throughput requirement in the video encoder, design challenges such as data dependence, external memory traffic, and on-chip memory area become even more critical. To solve these problems, we first propose an interlacing memory organization on the basis of quarter-LCU to resolve the data dependence between vertical and horizontal filtering of DF. The on-chip SRAM area is also reduced to about 25% on the basis of quarter-LCU scheme without throughput loss. We also propose a simplified bitrate estimation method of rate-distortion cost calculation to reduce the computational complexity in the mode decision of SAO. Our proposed hardware architecture of combined DF and SAO is designed for the HEVC intraencoder, and the proposed simplified bitrate estimation method of SAO can be applied to both intra- and intercoding. As a result, our design can support ultrahigh definition 7680 × 4320 at 40 f/s applications at merely 182 MHz working frequency. Total logic gate count is 103.3 K in 65 nm CMOS process.

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC

In this paper, a novel selective encryption image scheme based on JPEG2000 is proposed, which encrypts only the code-blocks corresponding to some sensitive precincts. In order to improve the security level we introduce the permutation of codeblocks contributing in the selected precincts. Symmetric encryption AES with CFB mode is used to encrypt swapped codeblocks.

The idea of combining permutation and selective encryption is used in order to minimize the amount of processed data encryption while ensuring the best possible degradation through the permutation.

The proposed process encryption doesn't introduce superfluous JPEG2000 markers in the protected codestream, i.e, the protected codestream format is compliant to JPEG2000 codestream one. It keeps file format and compression ratio unchanged and doesn't degrade the original error robustness. The proposed scheme works with any standard ciphers and introduces negligible computational cost.

A new selective encryption technique of JPEG2000 codestream for medical images transmission

In this paper, a novel selective encryption image scheme based on JPEG2000 is proposed, which encrypts only the code-blocks corresponding to some sensitive precincts. In order to improve the security level we introduce the permutation of codeblocks contributing in the selected precincts. Symmetric encryption AES with CFB mode is used to encrypt swapped codeblocks. The idea of combining permutation and selective encryption is used in order to minimize the amount of processed data encryption while ensuring the best possible degradation through the permutation. The proposed process encryption doesn't introduce superfluous JPEG2000 markers in the protected codestream, i.e, the protected codestream format is compliant to JPEG2000 codestream one. It keeps file format and compression ratio unchanged and doesn't degrade the original error robustness. The proposed scheme works with any standard ciphers and introduces negligible computational cost.

/pdf/a-new-selective-encryption-technique-of-jpeg2000-codestream-1806mhuhqu.pdf

An adaptive in-loop deblocking filter (DF) is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes a low power DF architecture with hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per macroblock (MB). In addition, the architecture utilizes the buffers efficiently to store the temporary data without affecting the standarddefined data dependency by a reasonable strategy of edge filtering order to enhance the reusability of the intermediate data. The system throughput can then be improved and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved when the proposed HESPA is enabled. Furthermore, the proposed architecture is implemented on a 0.18μm standard cell library, which consumes 19.8K gates at a clock frequency of 200 MHz, which compares competitively with other state-of-the-art works in terms of hardware cost.

/pdf/low-power-architecture-design-and-hardware-implementations-11i13nixqf.pdf

Low power architecture design and hardware implementations of deblocking filter in H.264/AVC

The paper proposes an efficient deblocking filter architecture for H.264/AVC. A four-stage pipeline has been adopted to boost the speed of deblocking filter process up to 192 clock cycles per one macroblock. Hybrid edge filter order enhances the reusability of intermediate data which not only increases system throughput, but also reduces power consumption because of diminishing memory access times. In addition, for saving power purpose, our architecture utilizes the buffers instead of SRAM on-chip for storing temporary data. Experimental results show that our design can achieve the throughput of 1146kMB/s while saving up to 25% power consumption when compared with previous design. The architecture is implemented in 0.18µm standard cell library, consumes 26.01 K gates at a clock frequency of 220MHz.

Low-power High-throughput Deblocking Filter Architecture for H.264/AVC

In this paper, we propose and verify an adaptive block watermarking algorithm based on JPEG2000 DWT, which determines watermarking for the original image by two scaling factors in order to overcome image degradation and blocking problem at the edge. Adaptive block watermarking algorithm uses 2 scaling factors, one is calculated by the ratio of present block average to the next block average, and the other is calculated by the ratio of total LL sub-band average to each block average. Signals of adaptive block watermark are obtained from an original image by itself and the strength of watermark is automatically controlled by image characters. Instead of conventional methods using identical intensity of a watermark, the proposed method uses adaptive watermark with different intensity controlled by each block. Thus, an adaptive block watermark improves the visuality of images by 4-14dB and it is robust against attacks such as filtering, JPEG2000 compression, resizing and cropping. Also we implemented the algorithm in ASIC using Hynix 0.25µm CMOS technology to integrate it in JPEG2000 codec chip.

http://www.wseas.us/e-library/conferences/2007beijing/papers/554-553.pdf

Adaptive block watermarking and its SOC implementation based on JPEG2000 DWT

Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2/sup r/- (2/sup l//spl plusmn/ 1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.

http://ieeexplore.ieee.org/iel5/10072/32297/01509927.pdf

A parity checker for a large residue numbers based on Montgomery reduction method

We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm.[11] We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 75,804 gates with 204,672 bits of RAM and 33,572 bits of ROM using 0.18um CMOS technology

8K-point Pipelined FFT/IFFT with Compact Memory for DVB-T using Block Floating-point Scaling Technique

We propose a 2K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-T (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 Single Path Feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm. We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58 dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 91800 gates with 184284 bits of Ram and 33572 bits of ROM using 0.18 um CMOS technology.

Hui-Gon Kim

Papers

Low-power High-throughput Deblocking Filter Architecture for H.264/AVC

Adaptive block watermarking and its SOC implementation based on JPEG2000 DWT

A parity checker for a large residue numbers based on Montgomery reduction method

8K-point Pipelined FFT/IFFT with Compact Memory for DVB-T using Block Floating-point Scaling Technique

8K-point pipelined FFT/IFFT with compact memory for DVB-T using block floating-point scaling technique