Precision is one of the most important aspects of manufacturing. High precision creates high quality, high performance, exchangeability, reliability, and added value for industrial products. Over the past decades, remarkable advances have been achieved in the area of high-precision manufacturing technologies, where the form accuracy is approaching the nanometer level and surface roughness the atomic level. These extremely high precision manufacturing technologies enable the development of high-performance optical elements, semiconductor substrates, biomedical parts, and so on, thereby enhancing the ability of human beings to explore the macro- and microscopic mysteries and potentialities of the natural world. In this paper, state-of-the-art high-precision material removal manufacturing technologies, especially ultraprecision cutting, grinding, deterministic form correction polishing, and supersmooth polishing, are reviewed and compared with insights into their principles, methodologies, and applications. The key issues in extreme precision manufacturing that should be considered for future R&D are discussed.

https://iopscience.iop.org/article/10.1088/2631-7990/ab1ff1/pdf

Manufacturing technologies toward extreme precision

EUVL holds the promise of returning to a high k1 lithography thereby reducing design and process complexity. First printed images from the EUV HVM tool generation that is being deployed in the field demonstrate the expected imaging quality; however, the industry is waiting to see if reliability data and productivity improvements of the first production tools at customer sites will meet expectations. While EUVL is still facing infrastructure and productivity challenges—mask blank defectivity and source power the most prominent among those—EUVL it is seen as the only technology that could meet the semiconductor industry's need to significantly reduce lithography cost from the double and multiple patterning approaches that are currently required to achieve the desired feature resolution.

http://ieeexplore.ieee.org/iel7/6828579/6839629/06839652.pdf

EUV Lithography

Diffraction-based overlay (DBO) accuracy is critical to the intelligent nanolithography process control for producing advanced semiconductor fabrication nodes. Optical gratings located on various layers are commonly used as the targets for the detection of the overlay displacement offset in DBO measurement. The asymmetry in intensity between the 1st and -1st beams diffracted by the targets is used for the prediction of grating displacement offset. This paper describes the effect of grating targets with sidewall angles (SWAs) on asymmetry in intensity and proposes an artificial neural network (ANN) method for enhancing the accuracy of grating displacement offset prediction. Grating targets with a 1:3 line-to-pitch ratio and SWA profiles varying from 86° to 90° were employed in this paper. The asymmetry in the intensity of the designed targets was computed for incident beams with transverse-electric and transverse-magnetic polarization at visible wavelength. An ANN feed-forward model was developed for the displacement offset prediction. The ANN, the conventional linear model, and the regression models were evaluated using diffraction data calculated by a numerical electromagnetic solver. The mean square error and the mean of the residual indicated that using the ANN model and incident beams at wavelengths of 600, 650, and 750 nm is substantially more effective for prediction than the conventional linear model is.

Artificial Neural Network for Diffraction Based Overlay Measurement

System-level line-edge roughness limits in extreme ultraviolet lithography Patrick P. Naulleau, 1 Dimitra Niakoula, 1 and Guojing Zhang 2 Center for X-Ray Optics, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 Intel Corporation, Santa Clara, CA 95052 Abstract As critical dimensions shrink, line edge and width roughness (LER and LWR) become of increasing concern. Traditionally LER is viewed as a resist-limited effect; however, as critical dimensions shrink and LER requirements become proportionally more stringent, system-level effects begin to play an important role. Recent advanced EUV resist testing results have demonstrated lower bounds on achievable LER at the level of approximately 2 to 3 nm. Here we use modeling to demonstrate that a significant portion of this low bound may in fact be do to system-level effects and in particular the mask. Of concern are both LER on the mask as well as roughness of the multilayer reflector. Modeling also shows roughness (flare) in the projection optics not to be of concern. Keyword: extreme ultraviolet, lithography, multilayer, mask, line-edge roughess

System-level line-edge roughness limits in extreme ultraviolet lithography

Contact holes (CHs) created by 193i lithography were shrunken by directed self-assembly of polystyrene-b-methylmethacrylate (PS-PMMA) block copolymers (BCPs). The placement error of these highly confined systems is determined both experimentally and by simulations. Good agreement between simulations (2 nm) and experiments was observed (2 nm). Extensive simulations show that the placement error is dependent on the length of the PS block only, indicating that the placement error is intrinsic to the BCP. This was explained by considering the BCPs as springs. For double CHs, a relation is found between the offset of the CH from the center of the CHs and the additional placement error.

Fundamental study of placement errors in directed self-assembly

Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV)
lithography, OPC is still needed to print the intended patterns on the wafer This is primarily because of new
non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 135nm, which must
be corrected by OPC So, for EUV, OPC is much more than conventional optical proximity correction This work
will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology
nodes The three error sources considered in this paper are flare, horizontal and vertical print differences, and
mask writing errors The OPC flow and computation requirements of EUV OPC are analyzed as well and
compared to DUV Conventional optical proximity correction is simpler and faster for EUV compared to DUV
because of the larger k1 factor But, flare and H-V biasing make exploitation of design hierarchy more difficult

EUV OPC for the 20-nm node and beyond

Flare (stray light) is an important effect impacting extreme ultraviolet lithography (EUVL) imaging system performance. Four flare measurement methods including Kirk, modulation transfer function, double exposure, and zonal ring approximation method are reviewed and analyzed theoretically. The point spread function of an EUV NXE:3100 exposure tool is extracted from the measured Kirk flare (KF) and fitted with a double-fractal model. The KF for this NXE:3100 tool is determined to be 8.5% for a 2-μm diameter absorber pad placed in a 12-mm outer radius bright field, which is larger than the previous 5% KF data measured by ASML and IMEC in 2011. The observation of the increased flare level in the NXE:3100 tool suggests that contamination of EUV optics may be a potential problem for EUVL manufacturing.

https://www.spiedigitallibrary.org/journals/Journal-of-MicroNanolithography-MEMS-and-MOEMS/volume-12/issue-4/042001/Review-of-resist-based-flare-measurement-methods-for-extreme-ultraviolet/10.1117/1.JMM.12.4.042001.pdf

Review of resist-based flare measurement methods for extreme ultraviolet lithography

The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.

Investigation of trench and contact hole shrink mechanism in the negative tone develop process

Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive investigation.

A Novel Method to Reduce Wafer Topography Effect for Implant Lithography Process

The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not sufficiently understood The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements A systematic study of the impact of mask LER correlation length ( ξ ), critical exponent ( α ) and standard deviation of the line edge ( σ ) on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated An experimentally relevant range of the three mask LER variables was explored in these simulations CDU and CER/LER were the primary metrics used to gauge printability and they were evaluated as a function of ξ, α and σ with stochastic simulations A 45nm pitch was investigated to determine critical mask LER parameters that mark printability transition regions relevant to the 7nm node middle of line

Hui Peng Koh

Papers

EUV OPC for the 20-nm node and beyond

Review of resist-based flare measurement methods for extreme ultraviolet lithography

Investigation of trench and contact hole shrink mechanism in the negative tone develop process

A Novel Method to Reduce Wafer Topography Effect for Implant Lithography Process

7nm node EUV predictive study of mask LER transference to wafer