Hung-Chih Chang

TL;DR: In this paper, the positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated and the stress-induced hump in the sub-threshold region is observed and is attributed to the edge transistor along the channel width direction.

TL;DR: A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width than rectangular fin, and have low punch-through current through the Si substrate.

TL;DR: A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width.

TL;DR: In this article, the gate dielectric has a leakage current ∼104X lower than other reported dielectrics in this EOT region, and the biaxial tensile strain of ∼0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the channel.

TL;DR: In this article, a record high peak mobility of ∼1050 cm2/V-s on (001) Ge substrate is demonstrated in NFET, which is ensured by rapid thermal oxidation (RTO) and remote ozone plasma treatment.