Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

TLDR: In this paper, the positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated and the stress-induced hump in the sub-threshold region is observed and is attributed to the edge transistor along the channel width direction.

Abstract: Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.