The proposed work concentrates on the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm ×0.8 mm is implemented in a 0.18 μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are − 113.76 and − 105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is − 187.2 dBc/Hz (decibels relative to carrier). Closed form equations allow for a performance driven design for both PLL and estimator. By using a variable sample frequency controlled by the PLL, the Kalman filter is always operated around its center frequency, which is the rated grid frequency. The new topology is compared to other published single-phase PLL designs and its operation is verified by both simulations and experiments. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. The PLL designed using dual mode logic technique exhibits excellent performance even under severely distorted utility grid voltage conditions. This robustness makes it very suitable for use in systems connected to grids having an important share of non-linear loads.

Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation

PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs

A fast locking technique for phase locked loop (PLL) is presented. In this technique the resistor of the filter is shorted, while the frequency switching occurs. A time to digital converter (TDC) measures the phase error at the phase frequency detector (PFD) output. The output of the TDC is used to control switches in the voltage control oscillator (VCO) to change the frequency in such a way that minimizes the phase error at the PFD output. Minimizing the phase error at the PFD output will create a zero, which stabilizes the PLL. The bandwidth (BW) is expanded by increasing the charge pump (CP) current. Here, the locking time reduces without stability problem. The simulation of proposed PLL in 180 nm CMOS technology shows a reduction of 75.9 µs locking time from 79 µs in conventional PLLs to 3.1 µs.

Fast locking technique for phase locked loop based on phase error cancellation

Fast locking adaptive PLL using Dual-Edge Phase-Frequency Detector

A low jitter phase-locked loop (PLL) based on self-biased techniques was designed. The PLL achieves process independent and low input tracking jitter. A novel cascode charge pump (CP) is realized to improve the current matching so as to reduce the jitter of the system. A capacitor is employed in the second CP to make third order PLL. The PLL is fabricated in SMIC 0.13 μm CMOS process, which achieves a very wide tuning range from 625MHz to 1.5GHz. And the phase noise of the VCO at 1MHz offset from the 1.25GHz only has −94.66 dBc/Hz. The measured RMS jitter and peak-to-peak jitter at 1.25GHz only have 3.53 ps and 21.19 ps.

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A low jitter phase-locked loop based on self-biased techniques

In this brief, a digital-control adaptive phase-locked loop (PLL) with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked. It uses a delay-independent threshold in a dual-slope transfer function to detect the locked state according to the counting result of the proposed TDC, which feeds to the BCU to switch the bandwidth of PLL. Then the PLL is switched from a wide loop bandwidth (6 MHz) to a narrow bandwidth (3 MHz) in the locked state. To verify the proposed scheme, the proposed adaptive PLL is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8 V. The measurement results show that the locking time is reduced by 67% while with a RMS jitter of only 8.79 ps when operating at 1.6 GHz.

Hwai-Pwu Chou

Papers

A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor