A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Nonvolatile memory device, operating method thereof and memory system including the same

Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

Non-volatile memory device, erasing method thereof, and memory system including the same

The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

Operating techniques for reducing program and read disturbs of a non-volatile memory

A non-volatile semiconductor memory device includes: a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and a plurality of sense amplifier circuits configured to read data from the memory cell array, wherein each the sense amplifier circuit is configured to sense cell data of a first memory cell selected from the memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to the first memory cell and written after the first memory cell.

Non-volatile semiconductor memory device and electric device with the same

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Nonvolatile memory devices, operating methods thereof and memory systems including the same

A memory string for using in an EEPROM device is provided which has two selection transistors and a plurality of depletion-type floating gate transistors whose drain-source paths are connected in series with each other between two selection transistors. The EEPROM device comprises a memory cell array including a plurality of bit lines arranged in columns and a plurality of memory strings arranged in rows and columns, each of memory strings in the same columns connected between the corresponding bit line and the ground; a row decoder for selecting memory strings in the same row and supplying predetermined voltages to control gates to the floating gate transistors in the selected memory strings according to a program, erase or read operation; a column decoder for coupling the bit lines to a data line according to the operation mode; means for precharging unselected bit lines during the program operation to a predetermined voltage so as to prevent erase of unselected floating gate transistors; a program control circuit connected to the data line for supplying a program voltage to the selected bit line during the program operation; and means for grounding all bit lines during the erase operation.

Depletion mode NAND string electrically erasable programmable semiconductor memory device and method for erasing and programming thereof

An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the floating gate transistors in the lower memory strings being respectively connected to first and second select lines, each other upper word lines, third and fourth select lines and each other lower word lines The drains of the first and second transistors are connected to the column line through a single contact hole; the other ends of the serial connections in the upper memory strings are connected to the reference line adjacent thereto; and means for connecting the other ends of the serial connections in the lower memory strings to the reference line adjacent thereto

EEPROM device with plurality of memory strings made of floating gate transistors connected in series

A data output buffer being capable of precharging a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in a semiconductor chip. The buffer includes means for minimizing the DC current consumption of a data bus precharge driver by feeding back an electric potential of an I/O port to an input of the precharging driver, and means for making the precharge driver operate during a specified period of time prior to providing the actual data by using an ATD pulse.

Data output buffer for use in semiconductor device

There is disclosed a programmable sequential code recognition circuit comprising an individual code recognition circuit for recognizing each input code, and a sequence recognition circuit for recognizing the sequency given for individual codes obtained by combination of input signals, so that a specific mode may be selected by the input combination sequentially inputted.

Programmable sequential-code recognition circuit

An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.

Hyung-Kyu Yim

Papers

Depletion mode NAND string electrically erasable programmable semiconductor memory device and method for erasing and programming thereof

EEPROM device with plurality of memory strings made of floating gate transistors connected in series

Data output buffer for use in semiconductor device

Programmable sequential-code recognition circuit

Error-bit generating circuit for use in a non-volatile semiconductor memory device