Jung-Dal Choi

TL;DR: In this article, the concept of floating-gate interference in flash memory cells was introduced for the first time and the floating gate interference causes V/sub T/ shift of a cell proportional to the V/ sub T/ change of the adjacent cells.

TL;DR: In this article, a semiconductor memory device is provided including first and second cell strings formed on a substrate, the first cell strings jointly connected to a bit line, and the second string selection unit of the second cell string has a channel dopant region.

TL;DR: A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program Cell (SLC) modes, is fabricated with a 0.15-/spl mu/m CMOS technology, achieving 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes.

TL;DR: In this article, a floating trap nonvolatile memory (FLVM) was proposed, where the memory devices include a semiconductor substrate and an adjacent gate electrode, and a charge storage layer between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant.

TL;DR: A 1 Gb NAND flash memory with 2b per cell uses 0.15 /spl mu/m CMOS and achieves simultaneous operation of 4 independent banks with 1.6 GMB/s program throughput.