This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents the fundamental background of the completion methodology, detailed explanation of the sensing circuitry operation, achieved simulation results as well as the comparison to state-of-the-art methods of completion detection.

Current sensing completion detection in dual-rail asynchronous systems

Power dissipation is one of the primary design constraints in modern digital circuits. From a magnitude of hand-held portable devices to big data analytics using highperformance computing, low energy dissipation is a key requirement for most modern devices. This paper showcases an elegant low power circuit design methodology based on Relative Timing driven asynchronous techniques. A low power MSP430 microprocessor design based on a novel asynchronous finite state machine implementation is presented. The design showcases the power benefits of the proposed asynchronous implementation over the synchronous counterpart and avoids major architectural modification which would directly influence the performance or power consumption. The implemented asynchronous MSP430 exhibits a minimum of 8x power benefit over the synchronous design for an almost identical pipeline structure and comparable throughput. The paper further elaborates on the novel asynchronous state machine implementation used for the design and presents an efficient method to design communicating asynchronous finite state machines in clock-less systems.

Design of a low power, relative timing based asynchronous MSP430 microprocessor

This dissertation presents the design of the most complex MTNCL circuit to date. A fully functional MTNCL MSP430 microcontroller is designed and benchmarked against an open source synchronous MSP430. The designs are compared in terms of area, active energy, and leakage energy. Techniques to reduce MTNCL pipeline activity and improve MTNCL register file area and power consumption are introduced. The results show the MTNCL design to have superior leakage power characteristics. The area and active energy comparisons highlight the need for better MTNCL logic synthesis techniques.

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Design and Analysis of an Asynchronous Microcontroller

Completion detection in dual-rail asynchronous systems by current-sensing

Balsa developed by Advanced Processor Technology(APT) Group of Manchester University presents robust design environment that supports both a framework for synthesizing asynchronous hardware systems and the language for describing such systems. In this paper, a design of microprocessor, MSP430, in balsa language and the functional verification of the controller is presented. Back-end retargeting is performed as a part of the design methodology in Balsa. By back-end retargeting procedure, a new technology library including FPGA cell library is incorporated into Balsa design environment. Moreover, the circuit area is analyzed and reduced in different implementation styles by replacing helpercells in balsa into standard cells of the target library.

Hyung-Woo Lee

Papers

Design of asynchronous MSP430 microprocessor using balsa back-end retargeting