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Proceedings ArticleDOI

Design of asynchronous MSP430 microprocessor using balsa back-end retargeting

TLDR
A design of microprocessor, MSP430, in balsa language and the functional verification of the controller is presented and back-end retargeting is performed as a part of the design methodology in Balsa.
Abstract
Balsa developed by Advanced Processor Technology(APT) Group of Manchester University presents robust design environment that supports both a framework for synthesizing asynchronous hardware systems and the language for describing such systems. In this paper, a design of microprocessor, MSP430, in balsa language and the functional verification of the controller is presented. Back-end retargeting is performed as a part of the design methodology in Balsa. By back-end retargeting procedure, a new technology library including FPGA cell library is incorporated into Balsa design environment. Moreover, the circuit area is analyzed and reduced in different implementation styles by replacing helpercells in balsa into standard cells of the target library.

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Citations
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Proceedings ArticleDOI

Current sensing completion detection in dual-rail asynchronous systems

TL;DR: The fundamental background of the completion methodology, detailed explanation of the sensing circuitry operation, achieved simulation results as well as the comparison to state-of-the-art methods of completion detection are presented.
Proceedings ArticleDOI

Design of a low power, relative timing based asynchronous MSP430 microprocessor

TL;DR: An elegant low power circuit design methodology based on Relative Timing driven asynchronous techniques is presented and an efficient method to design communicating asynchronous finite state machines in clock-less systems is presented.

Design and Analysis of an Asynchronous Microcontroller

Michael Hinds
TL;DR: This dissertation presents the design of the most complex MTNCL circuit to date, designed and benchmarked against an open source synchronous MSP430 microcontroller, and shows theMTNCL design to have superior leakage power characteristics.
Journal ArticleDOI

Completion detection in dual-rail asynchronous systems by current-sensing

TL;DR: Fundamental background of the completion detection methodology, detailed description of developed current sensor circuitry, achieved simulation results as well as the comparison with the state-of-the-art methods of completion detection and previous research that has been done in this scientific area are presented.
References
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Journal ArticleDOI

Communicating sequential processes

TL;DR: It is suggested that input and output are basic primitives of programming and that parallel composition of communicating sequential processes is a fundamental program structuring method.
Proceedings ArticleDOI

AMULET2e: an asynchronous embedded controller

TL;DR: An embedded system chip incorporating an enhanced asynchronous ARM core (AMULET2), a 4 Kbyte pipelined cache, a flexible memory interface and assorted programmable control functions, and innovative features that exploit its asynchronous operation to advantage in power-sensitive applications are described.
Journal ArticleDOI

TITAC: design of a quasi-delay-insensitive microprocessor

TL;DR: TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption for efficient signal generation and data transfer.
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