In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids — Optimization General Terms: Algorithms, Reliability

Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs

Counter-based power models have attracted the interest of researchers because they became a quick approach to know the insights of power consumption. Moreover, they allow one to overpass the limitations of measurement devices. In this paper, we compare different Top-down and Bottom-up Counter-based modeling methods. We present a qualitative and quantitative evaluation of their properties. In addition, we study how to extend them to support the currently ubiquitous dynamic voltage and frequency scaling (DVFS) mechanism. We propose a simple method to generate DVFS agnostic power models from the DVFS-specific models. The proposed method is applicable to models generated using any methodology and allows the reduction of the modeling time without affecting the fundamental properties of the models. The study is performed on an 18 DVFS states Intel® Core™ 2 platform using the SPECcpu2006, NAS and LMBENCH benchmark suites. In our testbed, a 6× reduction on the modeling time only increments 1% point on average the error in the predictions.

Counter-Based Power Modeling Methods

Clock power, skew and maximum latency are three key metrics for clock distribution in low-power and high-performance designs. An H-tree offers minimum clock skew and good robustness against variations, but at the cost of large wirelength and clock power. On the other hand, a “fishbone” clock network with spine-ribs structures has smaller wirelength, latency and clock power, but larger skew, as compared to an H-tree. No previous work enables systematic exploration of the regime between H-tree and spine to achieve an optimal tradeoff among clock power, skew, and latency. In this paper, we study the concept of a generalized H-tree (GH-tree)—a topologically balanced tree with an arbitrary sequence of branching factors—and propose a dynamic programming-based method to determine optimal clock power, skew, and latency, in the space of GH-tree solutions. Our method co-optimizes clock tree topology and buffering along branches according to fitted electrical models. We further propose a balanced ${K}$ -means clustering and a linear programming (LP)-guided buffer placement approach to embed the GH-tree with respect to a given sink placement. We validate our solutions in commercial clock tree synthesis (CTS) tool flows, in a commercial foundry’s 28LP technology. The results show up to 30% clock power reduction while achieving similar skew and maximum latency as CTS solutions from recent versions of leading commercial place-and-route tools. Our proposed approach also achieves up to 56% clock power reduction while achieving similar skew and maximum latency as compared to CTS solutions from a state-of-the-art academic tool.

https://par.nsf.gov/servlets/purl/10171002

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution

Accurate timing characterization of flip-flops is critical for robust circuit design. Conventionally, setup time and hold time are characterized independently, which results in pessimistic/optimistic designs. To reduce this pessimism/optimism, the interdependency between setup/hold-time has to be taken into account. Fast and accurate characterization of the setup/hold-time interdependency is however a challenging task. In this paper, an analytical model is proposed to capture the setup/hold-time interdependency in a conventional master-slave flip-flop. The accuracy of the proposed model is ∼10× higher than the previously published characterization methods. Furthermore, a flow is proposed to find the parameters of the model with ∼2.5× shorter computation time compared to the existing methods.

An analytical model for interdependent setup/hold-time characterization of flip-flops

Presently, almost all timing analyses and optimization tools are based on the strategy of setup and hold time constrained flip-flop timing model. However, this is a big mismatch with the timing characteristic of the real life flip-flops, which is so called flexible flip-flop timing, in which the clock-to-Q delay of every flip-flop may vary dynamically according to its setup and hold skews. This work addresses the problem of timing analysis and optimization based on flexible flip-flop timing model, in which the key contributions are (1) proposing a flexible flip-flop timing model based clock-to-Q delay range analysis, (2) exactly formulating the clock period minimization problem as a representative application, and (3) proposing a scalable speedup technique which is able to drastically reduce the run time with no or very little loss of timing optimality. Through experiments with benchmark circuits, it is shown that our timing analysis and optimization technique are able to consistently shorten the clock period or improve the timing yield of design, compared to that produced by the prior techniques.

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. Two commonly used strategies for solving the task are the scheduling of clock arrival times under bounded clock skew constraint and the scheduling of clock arrival times under hold and setup time constraints. This work belongs to the useful clock skew scheduling. In comparison with the prior works in which the inter-dependent relation between the setup and hold times of flip-flops have never been exploited, this work addresses the clock skew optimization problem integrated with the consideration of the interdependent relation between the setup and hold times, and clock-to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling algorithm in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period (T clk ) is shortened by 4.2% on average, namely the clock speed is improved from 369MHz∼2.23GHz to 385MHz∼2.33GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of T clk , respectively.

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing

Clock tree and clock mesh are two extreme structures of clock networks. Clock tree is good at saving clock wires and power, but is vulnerable to clock skew variation. On the other hand, clock mesh is good at mitigating clock skew variation, but spends considerable wires and power. Well known intermediate structures are clock tree with cross links and clock spine. This work addresses the problem automating the synthesis of clock spine networks. Unlike the clock tree with links between clock nodes, which is a sort of an incremental modification of the structure of clock tree, clock spine network is a completely separated structure from the structures of tree and mesh. Consequently, it is necessary and essential to develop a synthesis algorithm for clock spines, which will be compatible to the existing synthesis algorithms of clock trees and clock meshes. To this end, this work first addresses the problem of automating the synthesis of clock-gated clock spines with the objective of minimizing total clock power while meeting the clock skew and slew constraints. The key idea of our proposed synthesis algorithm is to identify and group the flip-flops with tight correlation of clock-gating operations together to form a spine while accurately predicting and maintaining clock skew and slew variations through the buffer insertion and stub allocation. Through experiments with benchmark circuits, it is shown our power-aware synthesis for clock spines uses significantly less power consumption compared to that of the conventional clock mesh synthesis algorithm at the expense of a little relaxed or the same constraint of clock skew.

Synthesis for Power-Aware Clock Spines

Dynamic voltage scaling (DVS) is one of the most effective techniques for reducing energy consumption on battery-operated embedded systems. According to the granularity of units to which voltage scaling is applied, the DVS problem can be divided into two subproblems: (i) inter-task DVS problem and (ii) intra-task DVS problem. A lot of effective DVS techniques have addressed either one of the two subproblems, but none of them have attempted to solve both simultaneously. This paper examines the problem of combined inter-and intra-task DVS, called the combined DVS (CDVS) problem. We solve the CDVS problem in two embedded system domains: one is systems with a sleep state and the other without sleep state. For systems without sleep state, we propose a close-to-optimal algorithm for the CDVS problem. We show that the algorithm is optimal when the power is a quadratically increasing function of the system's clock speed or the applied voltage level. For systems with a sleep state, we propose a refinement algorithm that fine-tunes the solution to the CDVS problem without sleep state to further reduce energy consumption by exploiting sleep state. Experimental results show that our proposed CDVS algorithm without sleep state is able to reduce the energy consumption by 12.5% on average over the results by the method that sequentially performs two existing inter-and intra-task DVS techniques, which are both optimal under no sleep state. Furthermore, our CDVS algorithm with a sleep state can reduce the energy consumption by 7.1% on average over the results by the conventional representative method that utilizes sleep state, but does not consider intra-and inter-task DVS simultaneously.

Algorithms for Combined Inter-and Intra-Task Dynamic Voltage Scaling

As the process variation is dominating to cause the clock timing variation among chips to be much large, it is widely accepted that post-silicon tunable (PST) clock buffers can effectively resolve the the clock timing violation. Since PST buffers, which can reset the clock delay to flip-flops after the chip is manufactured, imposes a non-trivial implementation area and control circuitry, it is very important to minimally allocate PST buffers while satisfying the chip yield constraint. In this work, contrary to the previous PST buffer allocation algorithms, in which the chip yield computation is performed by the (very slow) Monte-Carlo simulation, obliged to have a limited design space exploration of PST allocation, we (1) develop a graph-based chip yield computation technique which can update yields very efficiently and accurately for incremental PST buffer allocation, based on which we (2) propose a systematic (bottom-up and top-down with refinement) PST buffer allocation algorithm that is able to fully explore the design space of PST buffer allocation. Experimental results through benchmark designs show that our proposed PST buffer allocation with fast chip yield computation uses 28.5%~90.1% less number of PST buffers than that by the previous works while achieving four orders of magnitude run time improvement with less than 3%~5% of yield accuracy error.

Post-silicon tunable clock buffer allocation based on fast chip yield computation

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of ip-ops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate exible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period (Tclk) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

Hyungjung Seo

Papers

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing

Synthesis for Power-Aware Clock Spines

Algorithms for Combined Inter-and Intra-Task Dynamic Voltage Scaling

Post-silicon tunable clock buffer allocation based on fast chip yield computation

Post-Silicon Tuning Based on Flexible Flip-Flop Timing