Introduction to Electromagnetic Compatibility

Dramatic changes in the physical properties of composites occur when filler particles form a percolating network through the composite, particularly when the difference between the properties of the constitutive phases is large. By use of electric conductivity and dielectric properties as examples, recent studies on the physical properties of composites near percolation are reviewed. The effects of geometric factors and intrinsic properties of the fillers and the matrix, and especially of the interface between fillers and matrix, on electric and dielectric properties near percolation are discussed. Contact resistivity at the interface is less desirable for enhancing electrical conductivity. By contrast, an interface with high resistivity suppresses tunneling between adjacent fillers and leads to percolative composites with higher dielectric constant but lower dielectric loss. This review concludes with an outlook on the future possibilities and scientific challenges in the field.

Physical Properties of Composites Near Percolation

The mechanical flexibility and tunable properties of polymer-based materials make them attractive ones for a lot of applications. Exploring polymer-based dielectrics, such as ones used for capacitors and charge-storage applications, with high dielectric constant (high-j) has recently aroused considerable interest. Especially, motivated by higher function and further miniaturization of electronics, embedding (or integrating) polymer-based capacitors into the inner layers of organic printed circuit boards (PCBs) allows packaging substrate miniaturization and better electrical performance, which is a key for organic-based system-on-package technologies. But as capacitors, the relative dielectric constant j of general polymers (being good insulators) is too low (e.g., j< 5).Thus, a key issue is to substantially raise the dielectric constant of the polymers while retaining low dielectric loss. A few strategies have been developed to raise the j of polymer-based materials. A common approach is to add high-j ceramic fillers (e.g., BaTiO3) into a polymer. High loading of the ceramic fillers in the polymer composite, usually over 50 vol %, can increase j by about ten times relative to the polymer matrix, but dramatically decreases the adhesion of the composite (and increases its porosity) thus deteriorating the adaptability between the composite and the organic circuit boards. Another strategy is to fabricate percolative composite capacitors by using conductive fillers (e.g., metal particles). As the volume fraction f of the fillers increases to the vicinity of the percolation threshold fc, j of the composites can be dramatically enhanced as described by the well-known power law

High Dielectric Performance of Polymer Composite Films Induced by a Percolating Interparticle Barrier Layer

Методы подавления шумов и помех в электронных системах. (Noise reduction techniques in electronic systems)

European Union Risk Assessment Report

This paper describes the PCB power/ground plane edge radiation excited by a high-frequency clock, when it passes through power/ground plane pair by a through-hole signal via. For the analysis, the clock excitation mechanism was invested by TDR-TDT measurement and simulation with balanced TLM and via coupling model. Also, the power/ground plane edge radiation excited by sweeping from 100 MHz clock to 2900 MHz clock were measured. The power/ground plane edge radiation comes from voltage noise in the power/ground plane. From TDR-TDT investigations, we knew that a transition part in time domain makes the voltage noise, which has a strong relation with power/ground plane impedance depending on plane resonances and return current discontinuity of through-hole signal via. Therefore, the consecutive transitions of the clock make larger noise voltage and edge radiation. The PCB power/ground plane edge radiations of a clock depend on the power/ground plane impedance where the clock spectrum is varied. The higher power/ground plane impedance makes the larger power/ground plane edge radiation, when the clock frequency is fixed. In other words, the clock frequency and its harmonics go into the higher power/ground plane impedance range, the power/ground plane edge radiations are increased by maximum 35 dBm in near field measurement.

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PCB power/ground plane edge radiation excited by high-frequency clock

The modeling and simulation results about the IC and package power/ground network have been depicted. With the modeling for broadband frequency region, the effect of each part in power/ground network on IC and package was analyzed in frequency domain. Keywords-modeling; simulation; power/ground network; high frequency; IC and package

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Modeling and simulation of IC and package power/ground network

A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78ps/sub co/ jitter and under 240mV digital noise at 500MHz, while a conventional scheme has a 172ps/sub p-p/ jitter under the same conditions.

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

The return current path is the most critical part of high-speed interconnection design in both package and PCB. When the return current path is disturbed, significant amount of noise generation, coupling, and radiated emission problems occur. Signal vias and power/ground vias produce a return current path disconnect problem. In this paper, we demonstrate that the via is a major source of the SSN (simultaneous switching noise) generation, coupling, and edge radiated emission in multi-layer packages and PCBs.

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Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB

Signal integrity (SI) is affected by the location of via in the vicinity of slot. In multiple planar layer circuitry, when a signal trace changes layer through via, whether there is a slot in the reference plane beneath the signal trace or not has effects on signal integrity (SI). In this paper, the improved efficiency on signal integrity (SI) according to the location of via in the vicinity of slot is seen through simulation and measurement. The reduction of slot efficiency to provide isolation of a noise source from the rest of the PCB is also shown when a via is placed through the slot. Finally, design rule for the location of via in the vicinity of slot in the nearest reference plane is also discussed.

Hyungsoo Kim

Papers

PCB power/ground plane edge radiation excited by high-frequency clock

Modeling and simulation of IC and package power/ground network

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB

The Improvement of Signal Integrity (SI) according to The Location of Via in The Vicinity of A Slot in The Reference Plane