Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits.

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Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

System, method, and computer program product for improving memory systems

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of N = 128 and N = 256 nodes, respectively.

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3-D Topologies for Networks-on-Chip

Several interesting topologies emerge by incorporating the third dimension in the design of Networks-on-Chip (NoC). An analytic model for the zero-load latency of each network that considers the effect of the topology on the performance of a 3-D NoC is developed. A tradeoff between the number of nodes utilized in the third dimension of the network, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the processing elements (PE) of the network, which decreases the wire delay of the communication channel, is evaluated. A performance improvement of up to 33% is demonstrated for 3-D NoC as compared to a traditional 2-D NoC topology for a network size of N = 128 nodes.

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For high density and performance of microelectronic devices, the 3-D system in package (SiP) has been considered as a superb microelectronic packaging system. The development and evaluation of stacked chip type 3-D SiP with vertically interconnected TSV are reported. The process includes; 55 mum-diameter via holes by reactive ion etching (RIE), SiO2 dielectric layer by thermal oxidation, Ta and Cu seed layers by ionized metal plasma (IMP), Cu via filling by electroplating, Cu/Sn bump for multi-chip stacking and finally chip-to-PCB bonding with Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3-D SiP with 10 stacked chips was successfully fabricated. High frequency electrical model of the TSV was proposed and the model parameters were extracted from the measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. And then, contact resistances of Cu via and bump joint were discussed.

Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

In this paper, we show the electrical characteristics of TSV (through silicon via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon resistivity in case of single silicon substrate And we also show X-talk characteristics of two TSVs depending on distance of two signal TSVs and different locations of two signal TSVs and two ground TSVs in array type arrangement of TSV Additionally, we show the electrical characteristics of TSV depending on number of stacked TSVs All electrical characterizations on this paper are obtained using commercial 3-D full wave simulator and spice type circuit simulator such as HFSS of Ansoft Corporation and ADS of Agilent Corporation, respectively

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Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation

In this paper, we propose an equivalent circuit model of through wafer via which has height of 90 ?m and diameter of 75 ?m. The equivalent circuit model composed of RLCG components is developed based on the physical configuration of through wafer via. Then, the parameter values of the equivalent circuit model are fitted to the measured s-parameters up to 20GHz by parameter optimization method. The proposed model shows through wafer via is dominantly characterized by the capacitance of thin oxide around the via and resistive characteristic of lossy silicon substrate. From simulated TDR/TDT and eye-diagram waveforms of the proposed equivalent circuit model, it is found that parasitic effects of the via cause slow rising time of a signal during transmission of the signal to the through wafer via. However, unlike to the most cases, the slow rising time of through wafer via will not degrade signal integrity severely. At last, we show the effect of dimension of through wafer via on performance of signal transmission using 3-D full wave simulation.

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High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.

High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

Chunghyun Ryu

Papers

Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation

High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging

High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model