Mathematical details of a two-dimensional semiconductor device simulation program are presented, Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions, Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-three-dimensional device equivalent circuit model generation program are also discussed.

Two-dimensional device simulation program: 2DP

The physics of minority-carrier injection and internal quantum efficiency of heavily doped emitters is studied through a novel computer simulation. It is shown that in the shallow emitters of modern devices, the transport of carriers through the bulk of the emitter, and the surface recombination rate are the dominant mechanisms controlling the minority-carrier profile. Carrier recombination in the bulk of the emitter only produces a small perturbation of this profile. This observation permits us to develop a simple and accurate analytical model for the saturation current and internal quantum efficiency of shallow emitters.

The physics and modeling of heavily doped emitters

A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

Conventional numerical simulations of bipolar transistors assume that the carrier transport processes in the device can be described by the semiconductor equations with electric-field dependent mobility and the Einstein relation between the mobility and diffusion coefficient. These assumptions are not generally valid for the large electric fields, current densities, and concentration gradients present in advanced bipolar transistors. In this work, we present a new numerical bipolar device simulation which provides a better description of the carrier transport processes in these devices. Specifically, the carrier mobilities and diffusion coefficients are treated as functions of the average carrier energy and the thermoelectric current resulting from spatial variations in the carrier energies is included. The required carrier energies are calculated using energy balance equations. The results of this simulation are compared with those calculated using a conventional bipolar-device simulation, and the differences are discussed.

Numerical simulation of hot-carrier transport in silicon bipolar transistors

A device model investigation is made of power Si/GaP heterojunction gate-turn-off thyristors (GTOs), making use of previously published modeling tools, i.e. a one-dimensional model for GaAs/AlAs HBTs with a change in physical constants and a circuit simulator that allows the direct embedding of the one-dimensional model in an arbitrary circuit. By means of these modeling tools, design optimization is carried out for both homojunction and heterojunction GTOs. Comparison under the condition of an identical on-state voltage shows that the best heteroepitaxial GTO with an n-buffer layer exhibits an improvement in turn-off loss of a factor of 1.55 over the best homoepitaxial GTO of the same structure. This factor becomes 1.86 if a slight increase in the on-state voltage is permitted. >

A device model investigation of power Si/GaP heterojunction gate turn-off thyristors

A mathematical model has been formulated which solves semiconductor transport equations with heavy-doping corrections. This model requires only the device dimension and doping profile as input parameters. Model predictions agree very well with measured terminal characteristics of various NPN and PNP transistor structures and support heavy-doping parameters used in the model.

I. Antipov

Papers

Verification of heavy doping parameters in semiconductor device modeling