VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard cell and macro placement. Five major algorithms for placement are discussed: simulated annealing, force-directed placement, min-cut placement, placement by numerical optimization, and evolution-based placement. The first two classes of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. In each category, the basic algorithm is explained with appropriate examples. Also discussed are the different implementations done by researchers.

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VLSI cell placement techniques

We present a new routing region definition and ordering (RRDO) scheme for building block layout. Given an arbitrary placement of rectangular blocks (including the case with cycles in the channel precedence constraints), without modifying the placement, our scheme defines and orders channels so that when a new channel is being routed, its width can be expanded or contracted without destroying the previously routed channels. The cycles in the channel precedence constraints are broken by introducing a new kind of channel--the L-shaped channels. Unlike switchboxes, L-shaped channels can be expanded or contracted to permit the completion of routing without rerouting other existing channels. An efficient greedy RRDO algorithm has been implemented, which tries to generate as few L-shaped channels as possible since L-shaped channels are harder to route than straight channels. Our algorithm represents routing regions by a floor plan graph, for which we provide a precise definition and a construction algorithm. The experimental results of the RRDO algorithm are promising.

Routing Region Definition and Ordering Scheme for Building-Block Layout

A \emphk-stack layout (respectively, \emphk-queuelayout) of a graph consists of a total order of the vertices, and a partition of the edges into k sets of non-crossing (non-nested) edges with respect to the vertex ordering. A \emphk-track layout of a graph consists of a vertex k-colouring, and a total order of each vertex colour class, such that between each pair of colour classes no two edges cross. The \emphstack-number (respectively, \emphqueue-number, \emphtrack-number) of a graph G, denoted by sn(G) (qn(G), tn(G)), is the minimum k such that G has a k-stack (k-queue, k-track) layout.\par This paper studies stack, queue, and track layouts of graph subdivisions. It is known that every graph has a 3-stack subdivision. The best known upper bound on the number of division vertices per edge in a 3-stack subdivision of an n-vertex graph G is improved from O(log n) to O(log min\sn(G),qn(G)\). This result reduces the question of whether queue-number is bounded by stack-number to whether 3-stack graphs have bounded queue number.\par It is proved that every graph has a 2-queue subdivision, a 4-track subdivision, and a mixed 1-stack 1-queue subdivision. All these values are optimal for every non-planar graph. In addition, we characterise those graphs with k-stack, k-queue, and k-track subdivisions, for all values of k. The number of division vertices per edge in the case of 2-queue and 4-track subdivisions, namely O(log qn(G)), is optimal to within a constant factor, for every graph G. \par Applications to 3D polyline grid drawings are presented. For example, it is proved that every graph G has a 3D polyline grid drawing with the vertices on a rectangular prism, and with O(log qn(G)) bends per edge. Finally, we establish a tight relationship between queue layouts and so-called 2-track thickness of bipartite graphs. \par

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Stacks, Queues and Tracks: Layouts of Graph Subdivisions †

In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan" In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chip boundary shrinking The chip area estimation is performed by using individual block area calculations from empirically obtained equations A set of interactive commands is also provided to facilitate the manual optimization processes using a color graphic terminal By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan

CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design

We describe a method of constructing a B-rep solid model from a single hidden-line removed sketch view of a 3D object. The main steps of our approach are as follows. The sketch is first tidied in 2D (to remove digitisation errors). Line labelling is used to deduce the initial topology of the object and to locate hidden faces. Constraints are then produced from the line labelling and features in the drawing (such as probable symmetry) involving the unknown face coefficients and point depths. A least squares solution is found to the linear system and any grossly incompatible equations are rejected. Vertices are recalculated as the intersections of the faces to ensure we have a reconstructible solid. Any incomplete faces are then completed as far as possible from neighbouring faces, producing a solid model from the initial sketch, if successful. The current software works for polyhedral objects with trihedral vertices. CR Descriptors: I.3.5 [Computer Graphics]: Computational Geometry and Object Modelling Geometric algorithms, languages and systems; I.2.10 [Artificial Intelligence]: Vision and Scene Understanding Perceptual reasoning; I.3.6 [Computer Graphics]: Methodology and Techniques Interaction techniques; J.6 [Computer Applications]: CAE CAD.

Creating solid models from single 2D sketches

A hierarchical layout system for VLSI provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. Several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom LSI's.

SHARPS: A Hierarchical Layout System for VLSI

An automatic placement algorithm for standard cell and polycell LSI is described, which is constructed on the basis of heuristics for a set of interrelated placement subproblems. The algorithm is incorporated into a hierarchical layout system intended not only for standard cell and polycell LSI but for general cell LSI, by which standard cell and polycell LSI have begun to be laid out in practice. A part of implementation results are also shown to reveal how high the layout performance of the placement program.

A Placement Algorithm for Polycell LSI and its Evaluation

The requirement for high density packaging is dominant in the design of electronic systems. In the assembly of such systems multi-layer printed wiring boards are often used to provide the necessary connections among functional modules, and as the wiring density for a board ascends, an automatic scheme to realize 100 percent wiring would be more essential to reduce cost and time incurred in laying out wire pattern. Thus, methods to improve the layout of printed wiring boards are still continually under investigation.The present paper proposes an automatic layout system for two-layer printed wiring boards, which operates on a PDP 11/40 computer with 24K 16-bit words of core memory and with 1.2M words of disk storage, coupled with a TEKTRONIX 4014 display terminal in conjunction with a 4953 graphics tablet. This system has been at work, and more than 300 wiring boards of manufacturing use have been already processed automatically by this system, almost all with 100 percent routing realized. A part of such implemented results are also shown.

A minicomputerized automatic layout system for two-layer printed wiring boards

High density packaging is one of the most urgent requirements in the design of digital systems. In the assembly of such systems, printed wiring boards (PWB's) are used very often to provide the necessary interconnection among circuit modules. Thus, methods to raise wiring density of PWB's are continually under investigation. Given a router to realize 100 percent wiring, an efficient method for assigning logical gates to circuit modules and for determining the placement of the modules on a given PWB may contribute more toward raising the wirability than improving the existing routing scheme, especially when all available sophisticated routing algorithms have been attempted. The present paper proposes an algorithm to the problem of gate assignment and module placement, to be added to an existing router. It operates on a PDP 11/40 with 24K words core memory and 1.2M words disk storage coupled with a TEKTRONIX 4014 graphics terminal. We also show how effectively the described assignment and placement scheme improves the wirability of the router.

An Approach to Gate Assignment and Module Placement for Printed Wiring Boards

Recent advances in the packaging technology of microelectronics have changed the design rules for printed wiring boards (PWB's) such that the number of wiring tracks between adjacent pins of an ordinary dual in line package (DIP) is allowed to be two or more, and the number of signal layers to be laminated is often required to be four or more. When the packaging density or scale of a PWB augments to such an extent, conventional routing schemes are confronted with various difficulties. The present paper describes a new routing system which can cope with such high density PWB's, for which the maximum numbers of layers to be laminated, circuit modules to be mounted, and signal nets are admitted up to 16, 2,000 and 4,000, respectively. The system described operates on a PDP 11/34 computer coupled with a TEKTRONIX 4014 graphics terminal. A set of implementation results are also shown to reveal how much the described system contributes to the reduction of time and labor incurred in laying out multilayer PWB's of high density.

Ikuo Nishioka

Papers

SHARPS: A Hierarchical Layout System for VLSI

A Placement Algorithm for Polycell LSI and its Evaluation

A minicomputerized automatic layout system for two-layer printed wiring boards

An Approach to Gate Assignment and Module Placement for Printed Wiring Boards

An Automatic Routing System for High Density Multilayer Printed Wiring Boards