Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator

Fruit maturity is a critical factor in the supply chain, consumer preference, and agriculture industry Most classification methods on fruit maturity identify only two classes: ripe and unripe, but this paper estimates six maturity stages of papaya fruit Deep learning architectures have gained respect and brought breakthroughs in unimodal processing This paper suggests a novel non-destructive and multimodal classification using deep convolutional neural networks that estimate fruit maturity by feature concatenation of data acquired from two imaging modes: visible-light and hyperspectral imaging systems Morphological changes in the sample fruits can be easily measured with RGB images, while spectral signatures that provide high sensitivity and high correlation with the internal properties of fruits can be extracted from hyperspectral images with wavelength range in between 400 nm and 900 nm-factors that must be considered when building a model This study further modified the architectures: AlexNet, VGG16, VGG19, ResNet50, ResNeXt50, MobileNet, and MobileNetV2 to utilize multimodal data cubes composed of RGB and hyperspectral data for sensitivity analyses These multimodal variants can achieve up to 090 F1 scores and 145% top-2 error rate for the classification of six stages Overall, taking advantage of multimodal input coupled with powerful deep convolutional neural network models can classify fruit maturity even at refined levels of six stages This indicates that multimodal deep learning architectures and multimodal imaging have great potential for real-time in-field fruit maturity estimation that can help estimate optimal harvest time and other in-field industrial applications

Multimodal Deep Learning and Visible-Light and Hyperspectral Imaging for Fruit Maturity Estimation.

This paper presents a novel fully dynamic double tail dynamic comparator that exhibits low offset voltage compared to the traditional dynamic comparators. This paper comprises a novel fully differential double tail high performance comparator suitable for low-voltage low-power applications. A fully differential double tail comparator has been intended to meet the necessity of low offset voltage with optimum power with relatively high speed. In this paper expression for the calculation of the offset voltage and delay of the proposed comparator are derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of dynamic comparator by analyzing the influence of each transistor pair individually. Transistor mismatch analysis is carried out for offset voltage to fully explore the trade-offs in the design of comparator. The results are validated by Monte Carlo simulations and corner analysis. It is shown that in proposed comparator offset voltage is significantly reduced with optimum power. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180 nm CMOS technology with ?ý0.9 V supply. The Post-layout simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient and exhibits 91% low offset as compared with conventional comparator, which is the fastest among the conventional comparators.

A novel low offset low power CMOS dynamic comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

Recently, Cognitive-based Sentiment Analysis with emphasis on automatic detection of user behaviour, such as personality traits, based on online social media text has gained a lot of attention. However, most of the existing works are based on conventional techniques, which are not sufficient to get promising results. In this research work, we propose a hybrid Deep Learning-based model, namely Convolutional Neural Network concatenated with Long Short-Term Memory, to show the effectiveness of the proposed model for 8 important personality traits (Introversion-Extroversion, Intuition-Sensing, Thinking-Feeling, Judging-Perceiving). We implemented our experimental evaluations on the benchmark dataset to accomplish the personality trait classification task. Evaluations of the datasets have shown better results, which demonstrates that the proposed model can effectively classify the user’s personality traits as compared to the state-of-the-art techniques. Finally, we evaluate the effectiveness of our approach through statistical analysis. With the knowledge obtained from this research, organizations are capable of making their decisions regarding the recruitment of personals in an efficient way. Moreover, they can implement the information obtained from this research as best practices for the selection, management, and optimization of their policies, services, and products.

A Hybrid Deep Learning Technique for Personality Trait Classification From Text

This paper discusses the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed. This topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. This design will be focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves the comparator performance. Simulation results have been obtained using 0.18μm technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and 1.8V input range. Design has been carried out in SILVACO EDA tool, the schematic simulations are using Gateway SILVACO EDA tool and layout simulations are verified using Expert SILVACO EDA tool.

Low power CMOS charge sharing dynamic latch comparator using 0.18μm technology

This paper presents the comparative study on 8T SRAM with different type of sense amplifier. These sense amplifiers are voltage-mode sense amplifier (VMSA) and current-mode sense amplifier (CMSA). The first objective of this research is to design the 8T SRAM and sense amplifier and the next objective is to identify which design has better performance in term of power, speed, stability and area. Sense amplifiers are one of the most critical circuits in the periphery of CMOS memories that plays an important role to reduce the overall sensing delay and voltage. Earlier voltage mode sense amplifiers sense the voltage difference at bit and bit lines bar but as the memory size increase the bit line and date line capacitances increases. The tools used for simulation is SILVACO EDA Gateway and SILVACO EDA Expert for layout using 0.18um technology. The results show that the CMSA has higher speed with lower delay, and low power dissipation than VMSA. But, VMSA has smaller cell area and higher noise margin than CMSA. CMSA is more suitable for high speed performance and low power circuitry and VMSA is best suited for stability and smaller design.

Comparative study on 8T SRAM with different type of sense amplifier

Real-time image processing is related with typical frame rate that required processing all the frames as soon as the image is captured. Fast processing time is required for edge detection since it is needed to be carry out in a real time. This paper proposes a real-time edge detection technique for identifying Hevea leaves diseases (rubber tree leaves) in images and its hardware implementation. Three major Hevea leaves diseases which are Corynespora Leaf Spot, Bird's Eye Leaf Spot and Collectotrichum Leaf Disease used in this study for image comparison. The disease on the leaves can be detected through edge detection by using Sobel edge detection algorithm. The realtime edge detection result generated by FPGA Cyclone IV E which is displayed through a monitor is compared to Sobel edge detection algorithm that is generated with MATLAB. The algorithm has been implemented on FPGA and the image results on the VGA monitor are similar as the simulation on the MATLAB.

Real-time Hevea Leaves Diseases Identification using Sobel Edge Algorithm on FPGA: A Preliminary Study

This paper describes a comparative study of comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the conventional comparator is replaced with an open loop comparator and the non-ROM type encoder is used as the alternative for the conventional encoder. It is implemented using 0.18μm CMOS technology. Generally, the Silvaco Electronic Design Automation (EDA) tools is used for drawing the schematics, do the simulations and designing the layout of the proposed Flash ADC. The simulation results include 1.8V analog input range and 24.2662 mW of power dissipation at maximum sampling frequency of 500MHz with the lowest propagation delay time of 539.61ps.

Comparative study of comparator and encoder in a 4-bit Flash ADC using 0.18μm CMOS technology

Fast Fourier Transform (FFT) processor is the hardware implementation for FFT algorithms for Discrete Fourier Transform (DFT) which compute any signal in time domain to frequency domain. This processor plays an important role in many applications such as digital video broadcasting, wireless sensor network and many more digital signal processing applications, which requires a small area and low power processor. Pipelined FFT processor design on FPGA will speed up the design process and flexibility. This paper provides a survey of three types of pipelined FFT architecture, radix-8, radix-4 single path feedback (R4SDF) and radix-4 single-pasth delay commutator implemented on FPGA. The simulation part is done via Modelsim and verification through Matlab. While the implementation is done via Quartus on the Altera Cyclone IV FPGA board. The performance of these FFT processor is studied. The result shows that radix-8 pipelined FFT have higher power dissipation compared to R4SDF and R4SDC, however R4SDC design has low area design compared to the rest. Overall, all pipelined FFT processor designs are functioning accordingly.

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Ili Shairah Abdul Halim

Papers

Low power CMOS charge sharing dynamic latch comparator using 0.18μm technology

Comparative study on 8T SRAM with different type of sense amplifier

Real-time Hevea Leaves Diseases Identification using Sobel Edge Algorithm on FPGA: A Preliminary Study

Comparative study of comparator and encoder in a 4-bit Flash ADC using 0.18μm CMOS technology

Low Power Pipelined FFT Processor Architecture on FPGA