High Efficiency Video Coding (HEVC) is the latest joint standardization effort of ITU-T WP 3/16 and ISO/IEC JTC 1/SC 29/WG 11. The resultant standard will be published as twin text by ITU-T and ISO/IEC; in the latter case, it will also be known as MPEG-H Part 2. This paper describes the block partitioning structure of the draft HEVC standard and presents the results of an analysis of coding efficiency and complexity. Of the many new technical aspects of HEVC, the block partitioning structure has been identified as representing one of the most significant changes relative to previous video coding standards. In contrast to the fixed size 16 × 16 macroblock structure of H.264/AVC, HEVC defines three different units according to their functionalities. The coding unit defines a region sharing the same prediction mode, e.g., intra and inter, and it is represented by the leaf node of a quadtree structure. The prediction unit defines a region sharing the same prediction information. The transform unit, specified by another quadtree, defines a region sharing the same transformation. This paper introduces technical details of the block partitioning structure of HEVC with an emphasis on the method of designing a consistent framework by combining the three different units together. Experimental results are provided to justify the role of each component of the block partitioning structure and a comparison with the H.264/AVC design is performed.

Block Partitioning Structure in the HEVC Standard

High Efficiency Video Coding (HEVC) provides superior coding efficiency than previous video coding standards at the cost of increasing encoding complexity. The complexity increase of motion estimation (ME) procedure is rather significant, especially when considering the complicated partitioning structure of HEVC. To fully exploit the coding efficiency brought by HEVC requires a huge amount of computations. In this paper, we analyze the ME structure in HEVC and propose a parallel framework to decouple ME for different partitions on many-core processors. Based on local parallel method (LPM), we first use the directed acyclic graph (DAG)-based order to parallelize coding tree units (CTUs) and adopt improved LPM (ILPM) within each CTU (DAGILPM), which exploits the CTU-level and prediction unit (PU)-level parallelism. Then, we find that there exist completely independent PUs (CIPUs) and partially independent PUs (PIPUs). When the degree of parallelism (DP) is smaller than the maximum DP of DAGILPM, we process the CIPUs and PIPUs, which further increases the DP. The data dependencies and coding efficiency stay the same as LPM. Experiments show that on a 64-core system, compared with serial execution, our proposed scheme achieves more than 30 and 40 times speedup for 1920 × 1080 and 2560 × 1600 video sequences, respectively.

Efficient Parallel Framework for HEVC Motion Estimation on Many-Core Processors

The present disclosure pertains to an image-processing device and method that make it possible to suppress block noise. A βLUT_input calculator and a clip processor determine βLUT_input, which is a value inputted to an existing-β generator and an expanded-β generator. When the value of βLUT_input qp from the clip processor is 51 or less, the existing-β generator determines β using a LUT conforming to the HVEC standard, and supplies same to a filter process determination unit. When the value of βLUT_input qp from the clip processor is larger than 51, the expanded-β generator determines the expanded β and supplies same to the filter process determination part. This disclosure, for example, can be applied to an image processing device.

Image processing device and method

The emerging international standard of High Efficiency Video Coding (HEVC) is a successor to H.264/AVC. In the joint model of HEVC, the tree structured coding unit (CU) is adopted, which allows recursive splitting into four equally sized blocks. At each depth level, it enables up to 34 intra prediction modes. The intra mode decision process in HEVC is performed using all the possible depth levels and prediction modes to find the one with the least rate distortion (RD) cost using Lagrange multiplier. This achieves the highest coding efficiency but requires a very high computational complexity. In this paper, we propose a fast CU size decision and mode decision algorithm for HEVC intra coding. Since the optimal CU depth level is highly content-dependent, it is not efficient to use a fixed CU depth range for a whole image. Therefore, we can skip some specific depth levels rarely used in spatially nearby CUs. Meanwhile, there are RD cost and prediction mode correlations among different depth levels or spatially nearby CUs. By fully exploiting these correlations, we can skip some prediction modes which are rarely used in the parent CUs in the upper depth levels or spatially nearby CUs. Experimental results demonstrate that the proposed algorithm can save 21% computational complexity on average with negligible loss of coding efficiency.

Fast CU size decision and mode decision algorithm for HEVC intra coding

This paper analyzes the rate-distortion-complexity of High Efficiency Video Coding (HEVC) reference video codec (HM) and compares the results with AVC reference codec (JM). The examined software codecs are HM 6.0 using Main Profile (MP) and JM 18.0 using High Profile (HiP). These codes are benchmarked under the all-intra (AI), random access (RA), low-delay B (LB), and low-delay P (LP) coding configurations. In order to obtain a fair comparison, JM HiP anchor codec has been configured to conform to HM MP settings and coding configurations. The rate-distortion comparisons rely on objective quality assessments, i.e., bit rate differences for equal PSNR. The complexities of HM and JM have been profiled at the cycle level with Intel VTune on Intel Core 2 Duo processor. The coding efficiency of HEVC is drastically better than that of AVC. According to our experiments, the average bit rate decrements of HM MP over JM HiP are 23%, 35%, 40%, and 35% under the AI, RA, LB, and LP configurations, respectively. However, HM achieves its coding gain with a realistic overhead in complexity. Our profiling results show that the average software complexity ratios of HM MP and JM HiP encoders are 3.2× in the AI case, 1.2× in the RA case, 1.5× in the LB case, and 1.3× in the LP case. The respective ratios with HM MP and JM HiP decoders are 2.0×, 1.6×, 1.5×, and 1.4×. This paper also reveals the bottlenecks of HM codec and provides implementation guidelines for future real-time HEVC codecs.

Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video Codecs

Adaptive loop filtering for video coding is to minimize the mean square error between original samples and decoded samples by using Wiener-based adaptive filter. The proposed ALF is located at the last processing stage for each picture and can be regarded as a tool to catch and fix artifacts from previous stages. The suitable filter coefficients are determined by the encoder and explicitly signaled to the decoder. In order to achieve better coding efficiency, especially for high resolution videos, local adaptation is used for luma signals by applying different filters to different regions or blocks in a picture. In addition to filter adaptation, filter on/off control at coding tree unit (CTU) level is also helpful for improving coding efficiency. Syntax-wise, filter coefficients are sent in a picture level header called adaptation parameter set, and filter on/off flags of CTUs are interleaved at CTU level in the slice data. This syntax design not only supports picture level optimization but also achieves a low encoding latency. Simulation results show that the ALF can achieve on average 7% bit rate reduction for 25 HD sequences. The run time increases are 1% and 10% for encoders and decoders, respectively, without special attention to optimization in C++ code.

Adaptive Loop Filtering for Video Coding

In general, techniques are described for performing adaptive overlapped block motion compensation when coding video data. A video coding device configured to code video data may implement the techniques. The video coding device may comprise one or more processors configured to determine an adaptation metric from a region of support for one of a first partition and a second partition of one or more blocks of the video data separated by a partition boundary. The region of support may not be the entire one or more blocks of video data. The one or more processors may further be configured to adapt, based on the adaptation metric, application of an overlapped block motion compensation process to determine predicted pixel values near the partition boundary for a first predicted block representative of the first partition of the video block.

Adaptive overlapped block motion compensation

This paper describes a video coding technology proposal submitted by Qualcomm in response to a joint call for proposals (CfP) issued by ITU-T SG16 Q.6 (VCEG) and ISO/IEC JTC1/SC29/WG11 (MPEG) in January 2010. The proposed video codec follows a hybrid coding approach based on temporal prediction, followed by transform, quantization, and entropy coding of the residual. Some of its key features are extended block sizes (up to 64 × 64), single pass switched interpolation filters with offsets, mode-dependent directional transforms for intra-coding, luma and chroma high precision filtering, geometric motion partitions, adaptive motion vector resolution and efficient 16-point transforms. It also incorporates internal bit-depth increase and modified quadtree-based adaptive loop filtering. Simulation results are presented to demonstrate the high compression efficiency achieved by the proposed video codec at the expense of moderate increase in encoding and decoding complexity compared to the advanced video coding standard (AVC/H.264). For the random access and low delay configurations, it achieved average bit rate reductions of 30.9% and 33.0% for equivalent peak signal-to-noise ratio, respectively, compared to the corresponding AVC anchors. The proposed codec scored highly in both subjective evaluations and objective metrics and was among the best-performing CfP proposals.

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A Hybrid Video Coder Based on Extended Macroblock Sizes, Improved Interpolation, and Flexible Motion Representation

Techniques for performing sample adaptive offset (SAO) and adaptive loop filter (ALF) processes in a video coding process are described. The SAO and ALF processes may be combined. In one example, the determination of offset values for a SAO filter process may be based on classifications used in an ALF process. In one example, an ALF classification that indicates a particular directional characteristic of a video block may be used to determine how and whether an SAO filter process is applied to each sample within the video block.

Sample adaptive offset merged with adaptive loop filter in video coding

In one example, a video decoder is configured to store an adaptation parameter set (APS) data structure in a buffer of a coding device, wherein the APS data structure includes signaling data applicable to one or more slices of video data, decode at least one of the slices based on the signaling data of the APS data structure, after decoding the slice, determine that the APS data structure can be removed from the buffer, remove the APS data structure from the buffer based on the determination, and decode one or more additional slices of the video data after removing the APS data structure from the buffer.

In Suk Chong

Papers

Adaptive Loop Filtering for Video Coding

Adaptive overlapped block motion compensation

A Hybrid Video Coder Based on Extended Macroblock Sizes, Improved Interpolation, and Flexible Motion Representation

Sample adaptive offset merged with adaptive loop filter in video coding

Adaptation parameter sets for video coding