The present invention is directed towards a method and system for providing a technique referred to as flash caching to respond to requests for an object, such as a dynamically generated object, from multiple clients. This technique of the present invention uses a dynamically generated object stored in a buffer for transmission to a client, for example in response to a request from the client, to also respond to additional requests for the dynamically generated object from other clients while the object is stored in the buffer. Using this technique, the present invention is able to increase cache hit rates for extremely fast changing dynamically generated objects that may not otherwise be cacheable.

System and method for performing flash crowd caching of dynamically generated objects in a data communication network

An error decoding system that comprises a first Reed-Solomon (RS) decoder that receives an encoded codeword and generates a decoded codeword. An inner code (IC) decoder checks the decoded codeword for uncorrected errors. A decoding control module communicates with the first RS decoder and the IC decoder, iteratively modifies a parameter of the first RS decoder if the IC decoder detects uncorrected errors in the decoded codeword, and instructs the first RS decoder to decode the encoded codeword again after modifying the parameter.

Optimized Reed-Solomon decoder

The present invention discloses a method for generating a syndrome value of an error correction codeword (ECC), and a related apparatus. The ECC includes a fixed section, an information section, and a parity section. The fixed section includes not only byte “00”. The method provides a fixed syndrome value according to characteristics of the ECC. The syndrome value corresponding to the ECC is generated according to the fixed syndrome value, the information section, and the parity section.

Method for generating syndrome value and apparatus thereof

Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants derived from roots of the polynomial, and at least one counter that supplies an index. For each received symbol of the codeword, the multipliers multiply respective terms of the polynomial for a previous received symbol by constants from the source of constants, the counter advances to select respective products of the constants and the respective terms for the previous received symbol.

Continuous parallel cyclic BCH decoding architecture

A system and method used in a Reed-Solomon (RS) decoder for determining roots of error locator polynomials in which a first pre-computation operation is performed to obtain a p-bit polynomial solution value in a first clock cycle and second parallel feedback logical operations are performed to obtain a p-bit polynomial solution value in each subsequent clock cycles. The system excludes constant Galois Field multipliers from the critical timing path of the system so as to facilitate high speed error-locator polynomial root determination. In the case of an unshortened RS(m,d) decoder defined over the Galois Field GF(2p) where GF(2p) is a finite field of 2p elements and m=2p-1, final root location values are obtained in m cycles. In the case of a shortened RS(n,d) decoder defined over the Galois Field GF(2p) where GF(2p) is a finite field of 2p elements and m=2p-1 and n∫m, final root location values are obtained in n cycles.

Inderpol Deol

Papers

A high speed pre-computing circuit and method for finding the error-locator polynomial roots in a reed-solomon decoder