Showing papers by "Ingrid Verbauwhede published in 2000"
01 Jan 2000
TL;DR: An overview is given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems.
Abstract: Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSP's). In this tutorial, an overview is given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems. DSP processors have adapted instruction sets, memory architectures and data paths to execute compute intensive communications algorithms efficiently and in a low power fashion. Basic building blocks include convolutional decoders (mainly the Viterbi algorithm), turbo coding algorithms, FIR filters, speech coders, etc. This is illustrated with examples of different commercial and research processors.
24 citations
01 Aug 2000
TL;DR: An overview will be given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems.
Abstract: Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSPs). In this tutorial, an overview will be given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems. DSP processors have adapted instruction sets, memory architectures and data paths to execute compute intensive communications algorithms efficiently and in a low power fashion. Basic building blocks include convolutional decoders (mainly the Viterbi algorithm), turbo coding algorithms, FIR filters, speech coders, etc. This is illustrated with examples of different commercial and research processors. Please note that the authors do not endorse the processors used in this tutorial. These processors are used to illustrate how different solutions are proposed for the same problem.
16 citations
01 Jan 2000
TL;DR: The implementation of a turbo-decoding algorithm on the TMS320C55x processor with finite word lengths is described to reduce the state metric normalization time and to achieve at the same time an acceptable bit error rate (BER).
Abstract: Turbo codes are introduced in 3rd generation wireless cellular standards for their superior coding gain. The MIPS requirements of turbo codes are however extremely high. This paper describes the implementation of a turbo-decoding algorithm on the TMS320C55x processor. The coding performance is evaluated with fixed-point arithmetic. A method to optimize the memory is also introduced to address the large data storage problem. The effect of finite word lengths is carefully examined to reduce the state metric normalization time and to achieve at the same time an acceptable bit error rate (BER). The coding gain of 5.8 dB for a BER of 10/sup -3/ in 6 iterations is achieved with a frame size of 1 K bits and 50 Hz frame rate. Total MIPS estimate when using the max Log-MAP algorithm is 46 MIPS.
13 citations