Showing papers by "Iouliia Skliarova published in 2017"

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

Abstract: Abstract. The paper suggests and describes two architectures for parallel data sort. The first architecture is applicable to large data sets and it combines three stages of data processing: data sorting in hardware (in a Field-Programmable Gate Arrays – FPGA), merging preliminary sorted blocks in hardware (in the FPGA), and merging large subsets received from the FPGA in general-purpose software. Data exchange between the FPGA and a general-purpose computer is organized through a fast Peripheral Component Interconnect (PCI) express bus. The second architecture is applicable to small data sets and it enables sorting to be done at the time of data acquisition, i.e. as soon as the last data item is received, the sorted items can be transferred immediately. The results of experiments clearly demonstrate the advantages of the proposed architectures that permit the reduction of the required hardware resources and increasing throughput compared to the results reported in publications and software functions targeted to data sorting.

Data processing in the firmware systems for logic control based on search networks

Abstract: It was proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks were proposed, and the results of their theoretical and experimental comparison with the existing networks were presented.

Reconfigurable systems in engineering education: Best practices and future trends

Abstract: Advantages of reconfigurable systems and their importance for engineering education are reported in many publications. The paper presents recent results in this area that are achieved within long-term collaboration of two Universities: University of Aveiro in Portugal and Tallinn University of Technology in Estonia. Many alternative curricula have been analyzed and tested, and finally the following two-level strategy has been chosen: 1) an introductive segment on FPGA technology is given within the disciplines on digital design for the first year students; 2) a number of advanced courses, one of which is obligatory and the other optional, are given for the fourth and fifth year students. The paper discusses the methodology that has been developed and successfully realized. We also demonstrate advantages of both the proposed course structure and continuous evaluation with the main objective to disseminate the results.

Secure design of communication networks

Abstract: The paper is focused on increasing the security measures against malicious attacks by protecting hardware that exchange data. This is in contrast to studying or improving the existing methods that rely on only securing the data. We consider errors that may appear on a way between transmitting and receiving modules in different microelectronic devices and some of such errors may be injected by potential intruders (attackers). It is shown that although the known methods are sufficient they involve significant hardware resources and delays. We suggest detecting fault injection attacks through computing Hamming weights of each transmitting data combined with additional data created by a pseudo-random generator to be controlled by internal hardware of transmitting and receiving modules. Any generated number is known by the receiving and transmitting modules and it alters the final values of Hamming weights that can only be correctly recognized inside the transmitter/receiver. Our experiments have demonstrated that the proposed supplementary circuits allow the considered problem to be solved and they are very fast and moderate in resources.

Network-based priority buffer

Abstract: The paper suggests very fast electronic solutions for priority buffers that take data from many potential sources, accumulate them in a register, and output the most priority item in run time in such a way that as soon as a new value arrives it is included in the set with all previously received and untreated items and properly handled. It is shown that such circuits are required for real time embedded and cyber-physical systems. The buffer was first simulated in a Java program (in software) that allows to verify the intended functionality and then prototyped in hardware using commercially available prototyping boards with field-programmable gate arrays and up-to-date design environment, namely Vivado 2017.1. The best-known alternatives are briefly described and analyzed. The results of experiments have shown that the proposed solutions consume comparable hardware resources and are significantly faster. They may be used not only for priority management but also for real-time data sort.

Exploration of high-performance ports in Zynq-7000 devices with different traffic conditions

Abstract: This paper presents experimental results that allow high-performance ports in Zynq microchips to be evaluated taking into account parallel computations and their influence on throughput of FIR filters. All projects are based on Xilinx components. We found that although parallel traffic leads to performance degradation, actual throughput is reduced not very significantly. The results of experiments are discussed.

Fast Processing of Non-Repeated Values in Hardware

Abstract: The paper suggests a technique for fast data processing of unique and constrained items. The technique is based on two methods that involve: 1) address-based data sorting; and 2) communication-time networks. Input data are received one by one from a sequential channel. The first method enables undesirable values (e.g. previously taken or explicitly blocked) to be discarded. Although this method is chosen from the scope of data sorting, it is used in the paper (after some adjustments) for filtering. The second method enables each data item to be properly handled during communication time. For example, in case of data sorting it means that as soon as a new item is received it will immediately be placed in a proper position of the produced sorted subset that is composed of all previously acquired items. The circuits that implement the proposed methods have been entirely modeled and verified in software, then described in VHDL, synthesized and implemented in hardware, and finally evaluated. The results have shown that the proposed solutions are well suited for real-time applications.DOI: http://dx.doi.org/10.5755/j01.eie.23.3.18336

RAM-based mergers for data sort and frequent item computation

Abstract: Data sorting and frequent item computation are important tasks in data processing. The paper suggests an architecture for parallel data sorting with simultaneous counting of every item frequency. The architecture is designed for streaming data and incorporates data sorting in hardware, merging of preliminary sorted blocks with compressing of repeated items with calculating of repetitions in hardware, and merging large subsets received from the hardware in general-purpose software. Hardware merge components of this architecture count and compress repeated items in sorted subsets in order to reduce merging time and prepare the data for frequent item computation. The results of experiments clearly demonstrate advantages of the proposed architectures.