A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Double gate trench transistor

A novel signal scaling MESFET of a segmented dual gate design is disclosed. The MESFET, which is monolithically integrated on a semi-insulating substrate capable of localized surface modification to form active semiconductor regions using MMIC (monolithic microwave integrated circuit) techniques, has a small AC signal transfer which is adjustable in selected discrete steps. For operation in the gigahertz range, the substrate is preferably of gallium arsenide. In applying the MMIC technique, the MESFET, including segment electrodes and segment interconnections, and the electrical connections, signal paths, and passive components connected to the MESFET are formed on the substrate and defined by a photolithographic process. The technique permits reproducable feature definition and very compact minimum reactance segment interconnections, reducing deleterious parasitics and facilitating virtual unitary MESFET operation to very high frequencies. The signal scaling MESFET is an active MESFET subdivided into an n-fold plurality of selectively activated MESFET segments, each of a predetermined width, with dual gates for each segment. The AC input signal is applied to the first gates of all n segments and a DC control potential is selectively applied to the second activating gate of each of the n segments to turn current flow "ON" or "OFF" in selected segments. The MESFET transfer values so formed are each substantially constant in a small AC signal sense and successive values are stepped at intervals suitable for linear, trigonometric, logarithmic or arbitrary scaling functions.

Signal scaling MESFET of a segmented dual gate design

A method for manufacturing a semiconductor transistor device, specifically a Schottky barrier gate field-effect transistor, having an excellent performance at high frequency due to an exceedingly short gate length. An electrically conductive active layer is formed on a semi-insulating semiconductor substrate. Two adjacent walls are formed on the adjacent layer, are made of resist material, and extended linearly parallel to one another. Ohmic electrode metal is then evaporated obliquely with respect to the vertical surfaces of the two walls to form an ohmic electrode layer on the active layer in areas except for that lying between the two walls. A layer of Schottky barrier metal is then deposited between the two walls, and then the two walls are removed to remove the layers of ohmic electrode metal and Schottky barrier metal on the two walls.

Method of manufacturing Schottky field-effect transistors utilizing shadow masking

In a static induction transistor, the gate structure is split into two separate gates facing each other to cooperatively define therebetween a channel or channels of this transistor. One of these two separate gates is operative as a driving gate for driving the transistor in response to a driving signal applied thereto, while the other one is operative as a non-driving gate which has no driving signal applied. The non-driving gate may be held at a certain potential or floated. Such split-gate structure provides a higher operating speed of the transistor, and can be effectively applied to semiconductor memory devices. In such a memory device having split-gate structures, a plurality of field effect type semiconductor memory cells are formed perpendicular to a surface of a semiconductor wafer to enhance a high packing density of the memory device. Charge carriers are transported in the semiconductor bulk through channels defined by the split-gate structure, thereby enhancing a high-speed operation of the memory device.

Static induction transistor and its applied devices

A method of fabricating a self-aligned field-effect transistor having a T-shaped gate electrode and a sub-micron gate length. In the method of the present invention, a multi-layer gate structure is formed on an active region formed in a semiconductor substrate. A first aluminum layer of the gate structure, which is adjacent to the active region, is selectively etched to form a T-shaped gate electrode. The etching provides the first layer of the gate electrode with a gate length of less than 0.75 microns, and the T-shaped gate electrode is used as a shadow-mask to deposit self-aligned source and drain electrodes.

Method of fabricating self-aligned field-effect transistor having t-shaped gate electrode, sub-micron gate length and variable drain to gate spacing

A dual-gate Schottky barrier gate field effect transistor is provided with an intermediate electrode between a first and a second gate electrode. This intermediate electrode forms an ohmic contact with a semiconductor substrate of the transistor. The transistor is produced by etching a first film formed on a planar surface of the substrate by the use of a pair of mask pieces to leave a pair of gate electrodes narrower than the mask pieces and projecting a metal capable of forming an ohmic contact with the semiconductor towards the planar surface perpendicularly thereof. The projected metal provides source and drain electrode on both sides of the gate electrode pair and an intermediate electrode between the gate electrodes. The intermediate electrode may be left floating during operation.

Dual-gate schottky barrier gate fet having an intermediate electrode and a method of making same

Transistor a effet de champ a barriere de schottky a double porte

PURPOSE:To obtain a FET having low noise characteristics even in a microwave zone by forming an intermediate metallic film piece being in ohmic-contact with a semiconductor substrate between first and second Schottky barrier gate electrodes apart from the gate electrodes when a source electrode, the gate electrodes and a drain electrode are formed on the substrate with a flat surface and the bi-gate type FET is manufactured. CONSTITUTION:An N type GaAs layer 12 of a predetermined shape is formed on a high-resistance GaAs substrate 11, and the layer 12 is surrounded by an Al layer 13 generating a Schottky barrier to the layer 12. Photo-resist films 15-18 having prescribed patterns are formed on the surface of the layer 13, and columnar metallic film pieces consisting of the layers 13 are left under the films 15-18 through etching. An Au-Ge alloy being in ohmic-contact with the layer 12 is applied on the whole surface and isolated in the films 15-18 and under the films 15-18, and an alloy film piece 24 is formed between columnar metallic pieces 19 and 20 as gate electrodes shaped under the films 16 and 17. Film pieces 22 and 26 extending over the substrate 11 are also formed at both end sections of the layer 12 at the same time.

Ishikawa Masaoki

Papers

Dual-gate schottky barrier gate fet having an intermediate electrode and a method of making same

Transistor a effet de champ a barriere de schottky a double porte

Bi-gate-schottky barrier gate type field-effect transistor

Doppelgate-schottky-feldeffekttransistor mit zwischenelektrode und verfahren zu dessen herstellung