Disclosed are an organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device includes a thin-film transistor including source and drain electrodes, a first electrode formed by extending the source or drain electrode, a passivation layer and a bank insulation layer on the thin-film transistor configured to expose the first electrode so as to define an emission area, an organic light-emitting layer provided on the first electrode, and a second electrode configured to cover the organic light-emitting layer. The source or drain electrode includes a plurality of layers and the first electrode is integrally formed with any one layer portion of the source or drain electrode.

Organic light-emitting display device and method of manufacturing the same

An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region sequentially includes a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode; the peripheral circuit region sequentially includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer An orthogonal projection area of the second circuit line is at least partly overlapped with an orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer A method for manufacturing the array substrate and a display device including the array substrate are also disclosed

Array substrate and manufacturing method thereof, and display device

Gate dielectric plays an integral role in advancing the performance and reliability of GaN-based transistors. Si-alloying of aluminum oxide (Al2O3) dielectrics have been shown to provide a promising route to improve gate dielectric properties in GaN. In this letter, we report on the first demonstration of a GaN FET with aluminum silicon oxide (AlSiO) as the gate dielectric. Vertical normally-off GaN MOSFETs were fabricated on bulk GaN substrate. Excellent dc performance was achieved with a breakdown voltage of 1.2 kV, an ON-resistance of 2 $\text{m}\Omega $ .cm2, and a threshold voltage of 1.5 V (defined at $I_{\textsf {DS}} =1\,\,\mu \text{A}$ /mm). A high breakdown electric-field of 2.3 MV/cm was calculated in these devices. In addition to vertical GaN MOSFET results, a comparative study of Al2O3 and AlSiO-based in situ GaN MOS capacitors, including time-dependent dielectric breakdown characteristics is also presented.

First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET

https://iopscience.iop.org/article/10.7567/1882-0786/aaf62a/pdf

Hafnium silicate gate dielectrics in GaN metal oxide semiconductor capacitors

This work investigated characteristics of Al2O3/native oxide/n-GaN MOS capacitors by post-metallization annealing (PMA). A native oxide interlayer which composed of e- and γ-Ga2O3 phases (Native oxide) and the reduced amount of one (Reduced) on n-GaN were prepared by cleaning only a sulfuric acid peroxide mixture (SPM) and both SPM and buffered hydrofluoric acid, respectively. The effect of trimethylaluminum precursor on removal of a native oxide layer was not observed during Al2O3 deposition using atomic layer deposition. An as-grown capacitor (Native oxide) exhibited a small flatband voltage (V fb) hysteresis of ~30 mV and a large frequency dispersion, suggesting that the initial growth of the Al2O3 resulted in the formation of electrical defects on the GaN surface. Both the V fb hysteresis and frequency dispersion were drastically improved by PMA of the device at 300 °C. The positive fixed charge values (Q IL) estimated from the relationships between capacitance equivalent thickness and V fb were +6.1 × 1012 and +0.4–1.0 × 1012 cm−2 for as-grown and PMA-processed capacitors in the PMA temperature range of 300 °C–600 °C, respectively. The interface state density (D it) determined using a conductance method was also significantly reduced (by an order of magnitude) after PMA processing at 300 °C. These trends in the Q IL and D it data were observed in both the Native oxide and Reduced capacitors, indicating that this interlayer does not greatly affect fixed charge generation at the Al2O3/native oxide and Al2O3/modified native oxide interfaces. As a result, two types of treatments result in insignificant difference in the electrical properties of the capacitors.

https://iopscience.iop.org/article/10.1088/1361-6641/aafdbd/pdf

Characteristics of Al 2 O 3 /native oxide/n-GaN capacitors by post-metallization annealing

Al2O3/SiO2 nanolaminate for a gate oxide in a GaN-based MOS device

A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 50×1017 cm−3

Semiconductor device and method for producing same

This high electron mobility transistor is provided with: an electron transit layer (8), an electron supply layer (10), a recess (16), a gate insulating film (18), and a gate electrode (20). The electron transit layer is formed of a nitride semiconductor. The electron supply layer is formed of a nitride semiconductor having a band gap larger than that of the nitride semiconductor with which the electron transit layer is formed, and is laminated on the electron transit layer. The recess penetrates the electron supply layer from the upper surface of the electron supply layer, and reaches the electron transit layer. The insulating film covers the wall surfaces of the recess. The gate electrode is formed in the recess in a state wherein the gate electrode is covered with the gate insulating film. The bottom surface of the recess is formed of an n-type nitride semiconductor.

High electron mobility transistor

PROBLEM TO BE SOLVED: To achieve a semiconductor wafer where a group III nitride semiconductor layer has a flat surfaceSOLUTION: A semiconductor wafer 1 comprises a group III nitride semiconductor layer 10 provided on a substrate 2 via a multi-layer buffer layer 8 The multi-layer buffer layer 8 includes at least a first buffer layer 8a which contacts the group III nitride semiconductor layer 10 and a second buffer layer 8b which contacts the first buffer layer 8a and has a composition different from that of the first buffer layer 8a An average lattice constant of the multi-layer buffer layer 8 is smaller than that of the group III nitride semiconductor layer 10 In the semiconductor wafer 1, interface lattice distortion of the group III nitride semiconductor layer 10 at an interface of the group III nitride semiconductor layer 10 and the first buffer layer 8a is smaller than interface lattice distortion of the first buffer layer 8a at an interface of the first buffer layer 8a and the second buffer layer 8bSELECTED DRAWING: Figure 1

Itoh Kenji

Papers

Al2O3/SiO2 nanolaminate for a gate oxide in a GaN-based MOS device

Semiconductor device and method for producing same

High electron mobility transistor

Semiconductor wafer and semiconductor device