The invention discloses a novel synthesis method of 2, 3, 5, 6-tetramethylpyrazine and belongs to the technical field of synthesis of perfumes, medicines and pesticides. The reaction comprises addition, rearrangement, condensation and oxidation, which are performed in a reaction and sublimation route device, and a qualified product is obtained by steam distillation. According to the synthesis method disclosed by the invention, the process steps are simplified, material resources are fully utilized, and the synthesis method further has the advantages of low energy consumption, high product yield, environmental friendliness, low production cost, and simplicity and rapidness in operation, and is further conductive to industrial mass production. The synthesis method disclosed by the invention can be widely applied to industrial production of 2, 3, 5, 6-tetramethylpyrazine. By adopting the novel synthesis process disclosed by the invention, the 2, 3, 5, 6-tetramethylpyrazine product can be produced, and the 2, 3, 5, 6-tetramethylpyrazine product can be widely used as the perfume, a food additive, a photosensitizer, the medicine, the pesticide and the like.

Novel synthesis method of 2, 3, 5, 6-tetramethylpyrazine

A circuit for deriving an output clock signal from an input clock signal, the output clock 5 signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality o f latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of 10 the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.

Frequency divider circuits

PURPOSE:To attain stable circuit operation and to reduce the propagation time delay of an output side AND circuit by providing N-set of input terminals sectioned into plural groups, a parallel carry system multistage frequency division counter circuit and plural flip-flop circuits so as to synchronize an inter- block carry signal with a clock signal CONSTITUTION:Input bits D0-D5 are inputted simultaneously to a flip-flop circuit 9 when an external output signal F shows a '0' level, and the signal is frequency-divided into 1/2, 1/4, 1/81/64 respectively sequentially The three frequency division outputs of 1/2, 1/4 and 1/8 belonging to a group 1 are given to a 3-input AND circuit 13, where a count-up output is detected The signal output enters a D flip-flop circuit 14, where the re-timing is applied by using a clock signal CLK from a clock terminal 7 The accumulated delay time of each stage frequency counter circuit based on each delay element is cancelled by the re-timing effect and a carry signal in following with fidelity to the clock signal CLK is given to each stage of the frequency division counter belonging to a group II

Multi-stage frequency division binary counter

PURPOSE:To perform continuous rating time control over an ignition coil in time of accelerating in an accurate manner, by charging a condenser in accordance with a rising characteristic in a primary current, while generating an accelerating pulse according to the charging waveform, in case of a device performing the continuous rating time control of the ignition coil CONSTITUTION:In case of a controlling device 200 which inputs an input signal A commensurate to the continuous rating time found by an operational device (unillustrated here-in) at a previous stage, there is provided with a resistor 2230 or being an impedance element for detecting a primary current for an ignition coil 30, and a primary current waveform of the ignition coil 30 appearing as voltage of this resistor 2230 drops is made to be outputted via an amplifier 2410 In addition there is provided with a time constant device inclusive of a condenser 2470 to be charged so as to simulate a rising characteristic of the said primary current, and a charging voltage waveform of the condenser 2470 is compared with a reference voltage 2480 by a comparator 2490 And, an accelerating pulse is generated according to the charging waveform of the condenser 2470 whereby optimum continuous rating time is made so as to be secured in time of acceleration

Ignition controller for internal-combustion engine

PURPOSE:To increase operating speed by dividing N-bit constitution into two, high and low orders, and outputting a carry controlling a high-order bit counter from a low-order bit counter synchronously with a clock. CONSTITUTION:Since the N-bit constitution is divided into two, high and low orders, it is not required to control the countup of each bit up to the most significant bit, the number of fanouts and wiring length being increased toward low-order bits are reduced and high operating speed is obtained. Since a carry controlling the high-order bit counter 20 is outputted from the low-order bit counter 10 synchronously with a clock, the input number of NOR circuits NOR 11, 12 and NOR 14-16 constituting a countup control gate is nearly equal in the high-order bit counter 20 and the low-order bit counter 10 to each other, the number is nearly N/2 and high operating speed is attained.

Synchronous type programmable counter

PURPOSE:To obtain a frequency dividing circuit having a high-speed dividing function without producing any phase variance by providing a synchronizing FF having synchronism secured with a common clock between two cascaded dividers. CONSTITUTION:A synchronizing FF31 is put into a synchronizing part 24 formed between the 1st and 2nd stage divides 10 and 20. The synchronism is secured with a common clock among counters 11 and 21 of dividers 10 and 20, an FF13, an FF23 and the FF31. In order to set the phase variance of each stage at zero, the outputs of parts (k)-(m) and (i) of a counter 21 are controlled so that they appear in accordance with the output (f) of the FF13. For this purpose, the output (f) is applied to one of the inputs of an NOR gate 22. Furthermore no phase variance is produced at all since the synchronism is secured for FF13 and FF31 with a common clock.

Frequency dividing circuit

PURPOSE:To attain conference of M groups where maximum N people take part in by using a processing channel number of M(M=N/3)-set of voice processing sections with N as a maximum and with 3 as a minimum to make different in a conference telephone repeater having a total channel number of N. CONSTITUTION:The N-channel voice signals from an exchange are distributed into M groups at a conference group changeover section 1 and inputted to the voice processing section respectively. The voice processing for a conference telephone is conducted at voice processing sections 2-1, 2-2..., 2-M-1, 2-M, the processed voice signal is returned again to the conference group switching section 1, distributed again into the original channel configuration and returned to the exchange so as to attain the repeating of conference telephone. In this case, when the conference for 3, 4..., N people is used and the maximum conference number is used for n3, n4,..., nN, the relation of n3=[N/3], n4=[N/4], ..., nN= [M/N]=1 is established. The total number of channels is decreased in comparison with a conventional repeater using N processing channel for all voice processing sections.

Repeater for conference telephone

PURPOSE:To output a master clock having a center frequency by inputting a ground level with a switch when an input signal is interrupted so as to switch the clock frequency. CONSTITUTION:Switches 12, 13 are driven by a drive signal of a switch drive circuit 14 at the interruption of an input signal, a terminal D of an FF circuit 2 is grounded, a clock f2 is selected by the switch 13 and fed to the terminal D of an FF circuit 4 of a differentiation circuit 3. The clock f2 is a frequency division from the master clock from a master clock generator 8 at a frequency divider 15. On the other hand, the FF circuits 4 and 5 of the circuit 3 are operated while the output of the circuit 2 is brought to logical 1 by the clock f2 and a differentiation pulse is outputted, and the master clock is transmitted from an NAND gate 9 so as to have the center frequency.

Itou Atsuhiro

Papers

Frequency dividing circuit

Repeater for conference telephone

Digital pll circuit

Average power estimation circuit