A video server for providing Video-On-Demand is disclosed. A plurality of data sources are coupled individually to a first and second bi-directional data/instruction switch. The first switch is additionally coupled to a data storage system and the second switch is coupled to a network interface. A real time controller is coupled to the data sources and the switches and can couple any part of the data storage system to any selected data source and any given network channel to any selected data source. A control system coupled to the real time controller and the second switch provides support services to the real time controller and acts as a gateway to third party services and products. The data storage system is largely comprised of disk drive arrays. Video data is striped across the individual arrays, each video data program that a user requests being striped across one array. Each array provides video data to many users through the data sources. The video server is tolerant of individual failures in the data storage system and among the data sources, as operating portions of the data storage system and spare data sources can be rapidly switched to substitute for failed units. The server can also be readily expanded and provides a user experience similar to that of a video cassette recorder.

Video on demand system with multiple data sources configured to provide VCR-like services

The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.

Method for hashing in a packet network switching system

A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.

High speed single chip digital video network apparatus

The rapid growth of inter-networking and the popularity of ATM have resulted in a need for high-speed low-cost network components. This paper presents a new algorithm, Fair Arbitrated Round Robin (FARR), for scheduling the crossbar of a high-speed input-buffered switch. FARR respects virtual circuit (VC) priorities and has per-VC fairness properties that have previously only been achieved in output-buffered switches. Input-buffering is more cost-effective than output-buffering at high speeds, due to much more lenient memory speed requirements. Simulations are presented using a variety of work loads, traffic types and switch sizes. The simulations demonstrate the performance benefit of FARR over previous input-buffered switch algorithms and show that FARR performs similarly to Fair Prioritized Round Robin running on an output-buffered switch.

Fair prioritized scheduling in an input-buffered switch

Packets of data, some of which may carry a timestamp value, are transmitted through an Asynchronous Transfer Mode (ATM) network. Prior to transmission, each packet of data is encapsulated in a respective convergence sublayer protocol data unit (CS-PDU) having a header portion and a payload portion. The header portion of each CS-PDU contains a time correction indicator (TCI), which indicates whether the CS-PDU carries a packet of data having a timestamp value that may require correction after the CS-PDU passes through the network, and a time reference correction (TRC) field. Each CS-PDU is then segmented into a plurality of successive segments; a first one of the segments of each CS-PDU contains the CS-PDU header. Each segment is then inserted into the payload section of a respective ATM cell for transmission through the network. At each node in the network, cells are examined to determine if they contain a CS-PDU header. If a cell contains a CS-PDU header, any variable delays imposed upon that cell as it passed through the node are measured and added to the TRC field in the CS-PDU header prior to sending the cell to the next node. At a destination node, the accumulated TRC value may be added to the time stamp value of the packet carried in the CS-PDU in order to compensate for the variable delays imposed upon that packet as the cells carrying the packet traversed the network.

Methods and apparatus for time stamp correction in an asynchronous transfer mode network

Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.

Ivan P. Auer

Papers

Packet address look-ahead technique for use in implementing a high speed packet switch