Patent
Packet address look-ahead technique for use in implementing a high speed packet switch
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TLDR
In this paper, a fault tolerant packet switch (200) is proposed for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing crosspoints (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively).Abstract:
Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.read more
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References
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Journal ArticleDOI
A Broadband Packet Switch for Integrated Transport
J. Hui,E. Arthurs +1 more
TL;DR: A broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network is given and the throughput per port is improved by means of parallel switch fabric, while maintaining the periodic nature of the traffic.
Journal ArticleDOI
A survey of modern high-performance switching techniques
Hamid Ahmadi,W.E. Denzel +1 more
TL;DR: A survey of high-performance switch fabric architectures which incorporate fast packet switching as their underlying switching technique to handle various traffic types is presented.
Proceedings ArticleDOI
A shared buffer memory switch for an ATM exchange
TL;DR: A shared buffer memory switch in which output buffer memories are shared by all the switch output ports and are alloted to one particular output port as the occasion demands can further improve the hardware-utilization efficiency of the memory switch by increasing the buffer memory usage rate.
Patent
Congestion avoidance in high-speed network carrying bursty traffic
TL;DR: In this paper, a data communication network subject to bursty traffic employs a bandwidth allocation scheme to avoid congestion when a source node has a burst of traffic to send, it first sends a bandwidth request message through the network from source to destination At each intermediate node, this bandwidth request is examined and the node determines how much of the requested traffic level it will be able to support at a time in the future of one round-trip interval hence, and this node either grants the request or marks down the request to a level that it can support, then passes it on When the request
Proceedings ArticleDOI
Sunshine: a high performance self-routing broadband packet switch architecture
TL;DR: Results based on extensive simulations show that this architecture can achieve the extremely low cell loss rates necessary for circuit emulations, and is robust in a bursty environment.