A large number of factors such as the increasingly stringent pollutant emission policies, fossil fuel scarcity and their price volatility have increased the interest towards the partial or total electrification of current vehicular technologies. These transition of the vehicle fleet into electric is being carried out progressively. In the last decades, several technological milestones have been achieved, which range from the development of basic components to the current integrated electric drives made of silicon (Si) based power modules. In this context, the automotive industry and political and social agents are forcing the current technology of electric drives to its limits. For example, the U.S Department of Energy’s goals for 2020 include the development of power converter technologies with power densities higher than 14.1 kW/kg and efficiencies greater than 98%. Additionally, target price of power converters has been set below $3.3/kW. Thus, these goals could be only achieved by using advanced semiconductor technologies. Wide-bandgap (WBG) semiconductors, and, most notably, silicon carbide (SiC) based power electronic devices, have been proposed as the most promising alternative to Si devices due to their superior material properties. As the power module is one of the most significant component of the traction power converter, this work focuses on an in-deep review of the state of the art concerning such element, identifying the electrical requirements for the modules and the power conversion topologies that will best suit future drives. Additionally, current WBG technology is reviewed and, after a market analysis, the most suitable power semiconductor devices are highlighted. Finally, this work focuses on practical design aspects of the module, such as the layout of the module and optimum WBG based die parallelization, placement and Direct Bonded Copper (DBC) routing.

Power module electronics in HEV/EV applications: New trends in wide-bandgap semiconductor technologies and design aspects

The on-state resistance R
 ds,on
 is a key characteristic of unipolar power semiconductors and its value depends on the operating conditions, e.g. junction temperature, conducted current and applied gate voltage. Hence, the exact determination of the R
 ds,on
 value cannot rely on datasheet information and requires the measurement of current and on-state voltage during operation. Besides the determination of the conduction losses, the on-state voltage measurement enables dynamic R
 ds,on
 analysis, device temperature estimation, condition monitoring and consequently time-to-failure prediction. However, in contrast to a switch current measurement, several challenges arise in the design of an on-state voltage measurement circuit (OVMC), i.e. high measurement accuracy (mV-range) during on-state, high blocking voltage capability (kV-range) during off-state and fast dynamic response (ns-range) during switching transitions are demanded. Different OVMC concepts are known from IGBT applications, however, the more severe requirements introduced from the high switching frequency and low OV characterizing the operation of fast switching power semiconductors, prevent their usage. Off-the-shelf products hardly satisfy the mentioned specifications, whereas the performance of state-of-the-art OVM research prototypes require further investigations and/or improvements. With this aim, an innovative OVMC concept is designed, analyzed, calibrated and tested in this paper. Furthermore, the conduction losses of different power semiconductors are measured as function of their operating conditions to validate the performance and highlight the potential of the proposed OVMC.

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On-state voltage measurement of fast switching power semiconductors

The unprecedented performance potential of gallium nitride-on-silicon (GaN-on-Si) high electron mobility transistors (HEMTs) is seen as the key enabler for the design of power converters featuring extreme power density figures, as demanded in next-generation power electronics applications. However, unexpected loss mechanisms, i.e. dynamic $ {R}_{\text {ds,on}}$ phenomena and $ {C}_{\text {oss}}$ -losses, are appearing in currently available GaN transistors and are compromising their operation. In this paper, measurements of $ {C}_{\text {oss}}$ -losses are performed in a dedicated calorimetric measurement setup and, through a systematic approach, the root cause of the loss mechanism is potentially identified. Afterward, with the essential support of a manufacturer of power semiconductors, a novel transistor, featuring an enhanced multilayer III-N buffer, is developed according to the acquired knowledge. A significant reduction in terms of $ {C}_{\text {oss}}$ -losses, i.e. of soft-switching losses, and the absence of dynamic $ {R}_{\text {ds,on}}$ phenomena are verified experimentally on the new device. These achievements enable a significant performance improvement for future soft-switching power converters featuring GaN-on-Si HEMTs.

On the Origin of the $C_{\text{oss}}$ -Losses in Soft-Switching GaN-on-Si Power HEMTs

Figures-of-Merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material- and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a Figure-of-Merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridge-leg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.

/pdf/new-figure-of-merit-combining-semiconductor-and-multi-level-1zchoaak07.pdf

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

In this study, unique short-circuit failure mechanisms in 1.2-kV SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) at 400 and 800-V dc bias were investigated using experiments and numerical TCAD simulations, taking electrical, thermal, and mechanical stress into account. It was found that the fracture of the interlayer dielectric, caused by high mechanical stress due to different thermal expansion rates, is the source of failure in the 400-V short-circuit transient. The activation of the parasitic bipolar junction transistor under extreme high temperature was confirmed to be the failure mechanism in the 800-V short-circuit transient.

Investigations of SiC MOSFET Short-Circuit Failure Mechanisms Using Electrical, Thermal, and Mechanical Stress Analyses

Electrothermal modeling of silicon carbide (SiC) power devices is frequently performed to estimate the device temperature in operation, typically assuming a constant thermal conductivity and/or heat capacity of the SiC material. Whether and by how much the accuracy of the resulting device temperature prediction under these assumptions is compromised has not been investigated so far. Focusing on high-temperature operating conditions as found under short circuit (SC), this paper presents a comprehensive analysis of thermal material properties determining the temperature distribution inside SiC power mosfet s. Using a calibrated technology computer-aided design (TCAD) electrothermal model, it is demonstrated that the temperature prediction of SiC power devices under SC operation when neglecting either the top metallization or the temperature dependence of the heat capacity is inaccurate by as high as 25%. The presented analysis enables to optimize compact electrothermal models in terms of accuracy and computational time, which can be used to assess the maximum temperature of SiC power mosfet s in both discrete packages and multichip power modules exposed to fast thermal transients. A one-dimensional thermal network of a SiC power mosfet is proposed based on the thermal material properties, the size of the active area of the device, and its thickness.

/pdf/accurate-temperature-estimation-of-sic-power-mosfet-s-under-4ozuatcq3d.pdf

Accurate Temperature Estimation of SiC Power mosfet s Under Extreme Operating Conditions

Compact, light weight and efficient Power Electronic Building Blocks are seen as fundamental components of future More Electric Power Systems, e.g. More Electrical Aircraft. Core elements supporting the trend are power modules employing solely SiC MOSFETs. In order to take advantage of the high switching speed enabled by SiC, novel modules concepts must be investigated. For example, low inductance planar interconnection technologies, integrated buffer capacitors and damping networks are possible solutions to mitigate switching overvoltages and oscillations at the switching node occurring for conventional modules. In this paper, the analysis and the design of a novel ultra-low inductance 1200 V SiC power module featuring an integrated buffer-damping network are discussed. The power module is first described and characterized with impedance measurements. Afterwards, a general optimization procedure for the sizing and the selection of the integrated components is presented and measurements are performed to verify the analysis and to highlight the improvements of the proposed solution.

/pdf/analysis-and-design-of-a-1200-v-all-sic-planar-448yzmwj05.pdf

Analysis and design of a 1200 V All-SiC planar interconnection power module for next generation more electrical aircraft power electronic building blocks

Optimized low-inductive layouting of the package interconnections and external PCBs and bus-bars are necessary to benefit from Silicon Carbide (SiC) power devices, which allow inherently very fast switching transitions. In this paper, a comprehensive modeling procedure for highly accurate virtual dynamic characterization of discrete SiC power devices is described taking into account the 3D geometry of the internal and external interconnections of package as input. The modeling requirements are discussed on an example of a commercial 1.2 kV, 80 mΩ SiC Power MOSFET in a standard TO-247 package (Cree C2M0080120D). The software tools, Simplorer, Saber, Q3D and LTSpice, commonly used for modeling and simulation of power modules, are evaluated with respect to their modeling capabilities for SiC devices.

/pdf/highly-accurate-virtual-dynamic-characterization-of-discrete-4p8d05256f.pdf

Highly accurate virtual dynamic characterization of discrete SiC power devices

This paper introduces a new two-dimensional (2D) modeling approach for the fast calculation of inductor and transformer foil winding losses. The proposed modeling procedure is derived from the Partial Element Equivalent Circuit (PEEC) method, which is originally a full three-dimensional (3D) electromagnetic solution technique. With the presented modifications, the PEEC method can take into account the influence of an air gap fringing field and core material boundaries as well as skin- and proximity effect. A comparison to 2D Finite Element Method (FEM) simulations shows that the developed PEEC-based approach exhibits similar accuracy but shorter calculation times than the classical FEM modeling techniques typically employed for the calculation of non-uniform current distribution within foil windings. The new modeling approach is experimentally verified by calorimetric loss measurements of a gapped foil winding E-core inductor. Due to the fast calculation speed of the new approach, optimizations of inductive components with foil windings over a wide design space are finally possible.

A fast method for the calculation of foil winding losses

A major requirement for further development of wide-band gap (WBG) power devices and their applications is the optimization of packages and PCB layouts to enable fast-switching capabilities. Electromagnetic modelling allows the prediction of parasitic inductances, capacitances, and resistances of the current paths within power modules, which cannot be easily approached in measurements. As a result, electromagnetic-circuit-coupled modeling enables the optimization of package layouts and interconnections before manufacturing actual power modules. The accuracy and limitations of present numerical techniques for three-dimensional (3D) electromagnetic modeling of power modules is still neither well understood nor verified. This paper presents the extraction of parasitics of power semiconductor packages using two electromagnetic modelling approaches. The first approach is based on a well-established 3D electromagnetic quasi-static solver, ANSYS Q3D Extractor. For the second approach, a numerical solver based on the Partial Element Equivalent Circuit (PEEC) method is developed and assessed in terms of modelling accuracy required by fast switching WBG-based power converters. The PEEC method is presented as a promising numerical technique, which can potentially be used to overcome the limitations of the EM modeling based on the ANSYS Q3D Extractor.

/pdf/a-more-accurate-electromagnetic-modeling-of-wbg-power-mlu8tz9bpt.pdf

Ivana Kovacevic-Badstubner

Papers

Accurate Temperature Estimation of SiC Power mosfet s Under Extreme Operating Conditions

Analysis and design of a 1200 V All-SiC planar interconnection power module for next generation more electrical aircraft power electronic building blocks

Highly accurate virtual dynamic characterization of discrete SiC power devices

A fast method for the calculation of foil winding losses

A more accurate electromagnetic modeling of WBG power modules