Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.

EUV mask challenges and requirements for ultimate single exposure interconnects

The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a die-to-die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this paper, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed die-to-baseline reference die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7-nm BEOL layers. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of mask adder defects, while suppressing random process defects. This methodology has the potential to define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.

Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned Wafers

The reflective-mode EUV mask scanning lensless imaging microscope (RESCAN) is a synchrotron-based platform dedicated to EUV mask inspection and review at the Swiss Light Source. It is based on coherent diffraction imaging (CDI), which allows retrieving both the phase and the amplitude information of the mask surface. RESCAN has been successfully tested on masks with programmed phase and amplitude defects. A metrology method that can not only detect defects and contamination, but can also determine the material of the defects, can be a powerful tool to help identify the root cause of the defects. Here, we explore the possibility of leveraging the ability of RESCAN to detect the complex amplitude of the sample to distinguish surface defects of different materials. We fabricated a sample with random logic-like absorber patterns and pillar defects on top of a Mo/Si multilayer. We show our experimental results that show the defects of different materials exhibit specific contrast and phase values. This method can be used not only to detect the masks defects but also to identify the defect materials to a limited extent.

EUV mask defect material characterization through actinic lensless imaging

Extreme ultraviolet lithography (EUVL) patterned mask defect detection is a major issue that must be addressed to realize EUVL-based device fabrication. We have designed projection electron microscope (PEM) optics for integration into a mask inspection system, and the resulting PEM system performs well in half-pitch (hp) 16-nm-node EUVL patterned mask inspection applications. A learning system has been used in this PEM patterned mask inspection tool. The PEM identifies defects using the “defectivity” parameter that is derived from the acquired image characteristics. The learning system has been developed to reduce the labor and the costs associated with adjustment of the PEM’s detection capabilities to cope with newly defined mask defects. The concepts behind this learning system and the parameter optimization flow are presented here. The learning system for the PEM is based on a library of registered defects. The learning system then optimizes the detection capability by reconciling previously registered defects with newly registered defects. Functional verification of the learning system is also described, and the system’s detection capability is demonstrated by applying it to the inspection of hp 11-nm EUV masks. We can thus provide a user-friendly mask inspection system with reduced cost of ownership.

Enhanced defect detection capability using learning system for extreme ultraviolet lithography mask inspection tool with projection electron microscope optics

Increased capabilities in data storage and exploration provide significant insights for quality assurance in a high volume manufacturing environment. However, these opportunities are associated with great challenges in analytical model development, application deployment, system throughput and reliability. While no commercial software system fully meets the needs of recording head factories in Seagate, a novel strategy named optical inspection with centralized analysis has been developed to detect defects of trailing edges of the recording heads of hard disk drives, and fail the parts when necessary. Leveraging the state-of-the-art artificial intelligence technologies, a deep learning based semantic segmentation engine is built using convolutional neural networks for optical inspection. It has shown an improved accuracy to that of visual inspection performed by human. Meanwhile, a high performance computation engine has been built as a Kubernetes cluster with multiple GPU and CPU units. It is able to achieve the target throughput of three million high-resolution images in each day (i.e., 12 TB image data and 35 images per second). With the high fidelity offered by Kubernetes cluster, the developed applications (inference engine, preprocessor, postprocessor, etc.) serve as containerized microservices independently. Such an architecture ensures the vertical and horizontal scalabilities according to the computation of each individual deployment, while all deployments communicate through an Advanced Message Queuing Protocol cluster without human interference. This analytic framework enables Industry 4.0 recording head manufacturing by integrating advanced AI technologies with a robust edge computation architecture.

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Deep Learning based Optical Inspection with Centralized Analysis for High Volume Smart Manufacturing

Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing. In this work, we assess multiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

Ivy Wu

Papers

EUV mask and wafer defectivity: strategy and evaluation for full die defect inspection