A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2 . The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

Insulated gate field effect transistor having passivated schottky barriers to the channel

A method for producing hyperabrupt P± or N± regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant species begins with amorphizing the near-surface layer of a base crystal, and then implanting a steep retrograde distribution of the desired species into the amorphized layer, so that the retrograde distribution lies entirely within the amorphized layer, thereby avoiding channelling effects during implantation. The substantially defect-free structure of the base crystal is restored by annealing the implanted base crystal at a temperature sufficiently high to induce solid phase epitaxial regrowth on the underlying nonamorphized crystal, but at a temperature sufficiently low to avoid significant diffusion of the implanted species. The implanted species is subsequently activated by a rapid thermal annealing process, at a temperature sufficiently high to activate the implanted species, but for a very short time so that long-range diffusion does not occur. In a preferred embodiment, the implanted species is boron, BF 2 + , phosphorus, or arsenic in the top 0.20 micrometers of a substantially defect-free silicon base crystal, which may be in a bulk form or epitaxially deposited on an insulator substrate such as sapphire.

Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing

A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape clank each side of the gate trenches. A contact opening extends into the semiconductor regions between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at leaset a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.

Trenched-gate field effect transistors and methods of forming the same

A method for manufacturing a semiconductor device of a type in which a semiconductor element is formed on an insulating substrate. After ions which break the regularity of the crystal lattice of a monocrystalline semiconductor layer formed on the insulating substrate are implanted to form an amorphous semiconductor layer in part of the monocrystalline semiconductor layer, and after an impurity is doped in the semiconductor layer, a single annealing process is performed to recrystallize the amorphous semiconductor layer and at the same time to activate the doped impurity.

Method of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal state

A metal silicide contact to silicon devices which has broad application to almost all of the variety of silicon semiconductor devices is described. This contact with a substantial side component has particular advantage as the base contact for a bipolar transistor. However, contacts can be made to regions of any desired device regions with a variety of P+, N+, P, N, P-, N- and so forth conductivity types. Further, the contact can be an ohmic or Schottky contact.

Method of making integrated circuits using metal silicide contacts

A semi-conductor structure and particularly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths followed by very localized laser annealing to electrically reactivate the amorphous buried source and drain areas thereby providing effective vertical separation of the channel from the buried source and drain respectively. Accordingly, spatial separations between the self-aligned gate-to-drain, and gate-to-source can be relatively very closely controlled by varying the doping intensity and duration of the implantation thereby reducing the series resistance and increasing the operating speed.

Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain

A semiconductor structure and particularly a high-speed VLSI self-aligned Schottky Metal Semi-Conductor Field Effect Transistor having a relatively high operating frequency and low series resistance, predicated upon very controllable small structure geometries made by the growth of oxide bumper insulators on either side of the schottky barrier. The oxide bumpers width is relatively thicker than the depth of the initial silicon dioxide layer on the substrate surface thereby providing effective separation of the gate from the source and drain respectively. Accordingly, spatial separations between the self-aligned gate-and-drain and gate-and-source can be relatively very closely controlled by varying the doping level of an intermediate polysilicon layer thereby providing controllable differential polysilicon oxidation rates for the bumpers. Thus, the series resistance can be controlled to be relatively low thereby providing a VLSI SASMESFET device that can be operated at relatively high speeds.

Application of grown oxide bumper insulators to a high-speed VLSI SASMESFET

A semi-conductor structure and particulrly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths followed by very localized laser annealing to electrically reactivate the amorphous buried source and drain areas thereby providing effective vertical separation of the channel from the buried source and drain respectively Accordingly, spatial separations between the self-aligned gate-to-drain, and gate-to-source can be relatively very closely controlled by varying the doping intensity and duration of the implantation thereby reducing the series resistance and increasing the operating speed

Izya Bol

Papers

Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain

Application of grown oxide bumper insulators to a high-speed VLSI SASMESFET

Method of making a self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain