Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms.

As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

A Taxonomy of Hybrid Metaheuristics

We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. We then describe some basic techniques for various subtasks of high-level synthesis. Techniques that have been proposed in the past few years (since 1994) for various subtasks of high-level synthesis are surveyed. We also survey some new synthesis objectives including testability, power efficiency, and reliability.

Recent developments in high-level synthesis

High-level synthesis is comprised of interdependent tasks such as scheduling, allocation, and module selection. For today's very large-scale integration (VLSI) designs, the cost of solving the combined scheduling, allocation, and module selection problem by exhaustive search is prohibitive. However, to meet design objectives, an extensive design space exploration is often critical to obtaining superior designs. We present a framework for efficient design space exploration during high-level synthesis of datapaths for data-dominated applications. The framework uses a genetic algorithm (GA) to concurrently perform scheduling and allocation with the aim of finding schedules and module combinations that lead to superior designs while considering user-specified latency and area constraints. The GA uses a multichromosome representation to encode datapath schedules and module allocations and efficient heuristics to minimize functional and storage area costs, while minimizing circuit latencies. The framework provides the flexibility to perform resource-constrained scheduling, time-constrained scheduling, or a combination of the two, using a simple and fast list-scheduling technique. A graded penalty function is used as an objective function in evaluating the quality of designs to enable the GA to quickly reach areas of the search space where designs meeting user specified criteria are most likely to be found. Since GAs are population-based search heuristics, a unique feature of our framework is its ability to offer a large number of alternative datapath designs, all of which meet design specifications but differ in module, register, and interconnect configurations. Many experiments on well-known benchmarks show the effectiveness of our approach.

A genetic algorithm for the design space exploration of datapaths during high-level synthesis

MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design

This paper presents an integrated design space exploration of scheduling and allocation problem in high level synthesis using the heuristic based multi structure genetic algorithm. A cost function based on a combination of power consumption and pipelined execution time as well as a scheme to select functional unit type in case of multiple versions is proposed that can guide the genetic algorithm to near-optimal/optimal solution. The cost function model takes the functional units, registers, multiplexers and demultiplexers into consideration. The encoding process of the parent chromosome incorporates a special seeding process that enables the genetic algorithm to search for an optimal solution. This type of seeding process was specifically incorporated because the optimal solution to a problem always lies between the maximum serial and parallel implementation. Therefore it is always capable of finding a near-optimal/optimal solution to the combined problem of scheduling and allocation based on the provided user specified constraints. Results of the comparison with another recent genetic algorithm based exploration technique indicated considerable reduction of execution clock cycle as well as power consumption for almost all the benchmarks.

A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels

In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to cover other architectural issues and (for example) provides ways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods.

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High-level synthesis scheduling and allocation using genetic algorithms

http://ieeexplore.ieee.org/iel2/3478/10306/00486203.pdf

J. A. G. Jess

Papers

High-level synthesis scheduling and allocation using genetic algorithms

High-level synthesis scheduling and allocation using genetic algorithms