A display has a first array of pixels connected to emit individually-controlled amounts of light onto a second array of pixels. The second array of pixels is connected to pass individually-controllable portions of the light. The display has a controller connected to control the pixels of the first and second arrays of pixels. The controller is configured to control the pixels of the first array of pixels to provide on the second array of pixels an approximation of an image specified by image data; determine a difference between the image and the approximation of the image at individual pixels of the second array of pixels; and control the pixels of the second array of pixels to modulate the approximation of the image according to the corresponding determined differences.

High dynamic range display devices

A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.

Macroscalar processor architecture

A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream. A superscalar version of the processor is also described.

Apparatus and method for program level parallelism in a VLIW processor

Programmable processor and method with wide operations

Processor for executing wide operand operations using a control register and a results register

Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper four bits of the estimated partial remainder are ones while the fifth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.

Quotient digit selection logic for floating point division/square root

Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a re-order buffer, and third and fourth single precision operands are loaded into third and fourth respective rows of the re-order buffer. A first merge instruction copies the first and second single precision operands from respective first and second rows of the re-order buffer into first and second portions of a fifth row of the re-order buffer, thereby concatenating the first and second single precision operands to represent a first double precision operand. A second merge instruction copies the third and fourth single precision operands from respective third and fourth rows of the re-order buffer into first and second portions of a sixth row of the re-order buffer, thereby concatenating the third and fourth single precision operands to represent a second double precision operand. The first and second double precision operands stored in the fifth and sixth rows, respectively, of the re-order buffer are then provided directly to an associated FPU for execution.

Merging single precision floating point operands

In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0, and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

Three overlapped stages of radix-2 square root/division with speculative execution

Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. In the alternative case in which one or both of the fifth most significant carry or sum bits of the redundant partial remainder are ones, a quotient digit of one is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. An optimized five-level circuit is shown which implements the enhanced quotient selection function.

Correct and efficient sticky bit calculation for exact floating point divide/square root results

A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.

J. Arjun Prabhu

Papers

Quotient digit selection logic for floating point division/square root

Merging single precision floating point operands

Three overlapped stages of radix-2 square root/division with speculative execution

Correct and efficient sticky bit calculation for exact floating point divide/square root results

Exception handling for SIMD floating point-instructions using a floating point status register to report exceptions